IP Library Granted Patent US 8,483,291
Granted Patent B2
US 8,483,291 · App. 13/246,308 · Granted Jul 9, 2013

Analog to digital converter with increased sub-range resolution

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Quick Facts
Patent No.
US 8,483,291
App. No.
13/246,308
Granted
Jul 9, 2013
Kind
B2
Abstract

An analog to digital converter with increased sub-range resolution and method for using the analog to digital converter is described herein. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a plurality of sub-range ADCs, each sub-range ADC measuring the analog communication signal across at least one respective sub-range of the full-range, the plurality of sub-ranges extending across the full-range, a central sub-range ADC having greater quantization accuracy than at least one other sub-range ADC. The ADC also includes signal combining circuitry operable to process outputs of the plurality of sub-range ADCs to create the digital communication signal.

Claims (50)

1. A communication device comprising:

a processing module;

memory coupled to the processing module;

a communication interface coupled to the processing module, the communication interface comprising:

an analog front end that produces an analog communication signal;

a digital front end that receives a digital communication signal; and

an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range, the ADC comprising:

a plurality of sub-range ADCs, each sub-range ADC measuring the analog communication signal across at least one respective sub-range of the full-range, the plurality of sub-ranges extending across the full-range, a central sub-range ADC having a greater quantization accuracy than at least one other sub-range ADC; and

signal combining circuitry operable to process outputs of the plurality of sub-range ADCs to create the digital communication signal.

2. The communication device of claim 1 , wherein the central sub-range corresponds to an expected range of the analog communication signal.

3. The communication device of claim 1 , wherein the central sub-range corresponds to approximately a middle quarter of the full-range.

4. The communication device of claim 1 , wherein:

a first outer sub-range extends from an upper portion of the central sub-range to an upper portion of the full-range; and

a second outer sub-range extends from a lower portion of the central sub-range to a lower portion of the full-range.

5. The communication device of claim 1 , wherein:

the plurality of sub-range ADCs comprise the central sub-range ADC and an outer sub-range ADC; and

the outer sub-range ADC corresponds to the upper and lower portions of the full-range.

6. The communication device of claim 5 , wherein the central sub-range ADC and the outer sub-range ADC have a common bit size output.

7. The communication device of claim 1 , wherein the analog front end further comprises:

a Programmable Gain Amplifier (PGA) responsive to a gain input and operable to gain adjust the analog communication signal; and

gain control circuitry operable to produce the gain input so that the analog communication signal is within an expected range.

8. The communication device of claim 1 , wherein the communication interface is operable to service Powerline Communications.

9. The communication device of claim 1 , wherein the ADC further comprises range adjusting circuitry operable to select the respective sub-ranges serviced by the plurality of sub-range ADCs.

10. A method for operating a communication device comprising:

producing an analog communication signal by an analog front end;

sampling the analog communication signal across a full-range by a plurality of sub-range ADCs, each sub-range ADC measuring the analog communication signal across at least one respective sub-range of the full-range, the plurality of sub-ranges extending across the full-range, a central sub-range ADC having a greater quantization accuracy than at least one other sub-range ADC; and

processing outputs of the plurality of sub-range ADCs to create a digital communication signal.

11. The method of claim 10 , wherein the central sub-range corresponds to an expected range of the analog communication signal.

12. The method of claim 10 , wherein the central sub-range corresponds to approximately a middle quarter of the full-range.

13. The method of claim 10 , wherein:

a first outer sub-range extends from an upper portion of the central sub-range to an upper portion of the full-range; and

a second outer sub-range extends from a lower portion of the central sub-range to a lower portion of the full-range.

14. The method of claim 10 , wherein:

the plurality of sub-ranges comprise the central sub-range and an outer sub-range; and

the outer sub-range corresponds to the upper and lower portions of the full-range.

15. The method of claim 14 , wherein the central sub-range ADC and the outer sub-range ADC have a common bit size output.

16. The method of claim 10 , further comprising gain adjusting the analog communication signal in an attempt to cause the analog communication signal to be in an expected range.

17. The method of claim 10 , wherein the analog communication signal is a Powerline Communication signal.

18. The method of claim 10 , further comprising adjusting the respective sub-ranges of the plurality of sub-range ADCs.

19. An Analog to Digital Converter (ADC) that samples an analog signal across a full-range, the ADC comprising:

a plurality of sub-range ADCs, each sub-range ADC measuring the analog signal across a respective sub-range of the full-range, the plurality of sub-ranges extending across the full-range, a central sub-range ADC having a greater quantization accuracy than at least one other sub-range ADC; and

signal combining circuitry operable to process outputs of the plurality of sub-range ADCs to create a digital signal.

20. The ADC of claim 19 , wherein the central sub-range corresponds to an expected range of the analog signal.

21. The ADC of claim 19 , wherein:

a first outer sub-range extends from an upper portion of the central sub-range to an upper portion of the full-range; and

a second outer sub-range extends from a lower portion of the central sub-range to a lower portion of the full-range.

22. The ADC of claim 19 , wherein:

the plurality of sub-range ADCs comprise the central sub-range ADC and an outer sub-range ADC; and

the outer sub-range ADC corresponds to the upper and lower portions of the full-range.

23. The ADC of claim 22 , wherein the central sub-range ADC and the outer sub-range ADC have a common bit size output.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2011
From: FINDLATER, KEITH; DANESH, SEYED AA; HURWITZ, JONATHAN EPHRAIM DAVID
To: BROADCOM CORPORATION
Reel/Frame 026979/0348 →