System comprising a semiconductor device and structure
View Patent ↗A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor.
1. A semiconductor device, comprising:
a first semiconductor layer comprising first transistors, wherein said first transistors are interconnected by at least one metal layer comprising aluminum or copper; and
a second mono-crystallized semiconductor layer comprising second transistors and overlaying said at least one metal layer,
wherein said at least one metal layer is in-between said first semiconductor layer and said second mono-crystallized semiconductor layer,
wherein said second mono-crystallized semiconductor layer is less than 150 nm in thickness, and
wherein at least one of said second transistors is an N-type transistor and at least one of said second transistors is a P-type transistor.
2. A semiconductor device according to claim 1 , further comprising:
a plurality of connection paths between said second transistors and said first transistors,
wherein said plurality of connection paths comprise vias through said second mono-crystallized semiconductor layer, and
wherein at least one of said vias is less than about 150 nm in diameter.
3. A semiconductor device according to claim 1 , further comprising:
a plurality of connection paths between said second transistors and said first transistors, and said first semiconductor layer comprising first alignment marks,
wherein at least one of said connection paths has a contact to said second transistors, and
wherein said contact is aligned to one of said first alignment marks.
4. A mobile phone comprising a semiconductor device according to claim 1 .
5. A semiconductor device according to claim 1 ,
wherein said second transistors form at least one second circuit,
wherein said first transistors form a first circuit substantially the same as the second circuit, and
the semiconductor device further comprises:
a switch operable to cause one of said first and second circuits to be replaced by the other of said first and second circuits.
6. A semiconductor device according to claim 1 , further comprising:
a heat spreader between said first semiconductor layer and said second mono-crystallized semiconductor layer.
7. A semiconductor device according to claim 1 wherein at least one of said second transistors is one of:
(i) a recessed-channel transistor (RCAT);
(ii) a junction-less transistor;
(iii) a replacement-gate transistor;
(iv) a thin-side-up transistor;
(v) a double gate transistor; or
(vi) a horizontally oriented transistor.
8. A semiconductor device comprising:
a first semiconductor layer comprising first transistors, wherein said first transistors are interconnected by at least one metal layer comprising aluminum or copper;
a second mono-crystallized semiconductor layer comprising second transistors and overlaying said at least one metal layer,
wherein said at least one metal layer is in-between said first semiconductor layer and said second mono-crystallized semiconductor layer; and
a plurality of connection paths between said second transistors and said first transistors,
wherein said plurality of connection paths comprise vias through said second mono-crystallized semiconductor layer,
wherein at least one of said vias is less than about 150 nm in diameter, and
wherein said second transistors comprise horizontally oriented transistors.
9. A semiconductor device according to claim 8 , further comprising:
a plurality of connection paths between said second transistors and said first transistors, and said first semiconductor layer comprising first alignment marks,
wherein at least one of said connection paths has a contact to said second transistors, and
wherein said contact is aligned to one of said first alignment marks.
10. A semiconductor device according to claim 8 wherein said second mono-crystallized semiconductor layer is less than about 150 nm in thickness.
11. A mobile phone comprising a semiconductor device according to claim 8 .
12. A semiconductor device according to claim 8 wherein said second transistors comprise a plurality of N-type transistors and P-type transistors.
13. A semiconductor device according to claim 8 , further comprising:
a heat spreader between said first semiconductor layer and said second mono-crystallized semiconductor layer.
14. A semiconductor device according to claim 8 wherein at least one of said second transistors is one of:
(i) a recessed-channel transistor (RCAT);
(ii) a junction-less transistor;
(iii) a replacement-gate transistor;
(iv) a thin-side-up transistor; or
(v) a double gate transistor.
15. A semiconductor device comprising:
a first semiconductor layer comprising first alignment marks and first transistors, wherein said first transistors are interconnected by at least one metal layer comprising aluminum or copper;
a second mono-crystallized semiconductor layer comprising second transistors and overlaying said at least one metal layer, wherein said at least one metal layer is in-between said first semiconductor layer and said second mono-crystallized semiconductor layer, and
a plurality of connection paths between said second transistors and said first transistors,
wherein said second transistors comprise horizontally oriented transistors, and
wherein at least one of said connection paths has a contact to said second transistors wherein said contact is aligned to one of said first alignment marks.
16. A semiconductor device according to claim 15 wherein said second mono-crystallized semiconductor layer is less than about 150 nm in thickness.
17. A mobile phone comprising a semiconductor device according to claim 15 .
18. A semiconductor device according to claim 15 wherein said second transistors comprise a plurality of N-type transistors and P-type transistors.
19. A semiconductor device according to claim 15 ,
wherein said second mono-crystallized semiconductor layer comprises a plurality of thermal contacts, and
wherein said thermal contacts are adapted to conduct heat but not electric current.
20. A semiconductor device according to claim 15 , further comprising:
a heat spreader between said first semiconductor layer and said second mono-crystallized semiconductor layer.
21. A semiconductor device according to claim 15 , further comprising:
a plurality of connection paths between said second transistors and said first transistors,
wherein said connection paths comprise vias through said second mono-crystallized semiconductor layer, and
wherein at least one of said vias is less than about 150 nm in diameter.
22. A semiconductor device according to claim 15 wherein at least one of said second transistors is one of:
(i) a recessed-channel transistor (RCAT);
(ii) a junction-less transistor;
(iii) a replacement-gate transistor;
(iv) a thin-side-up transistor; or
(v) a double gate transistor.
23. A 3D IC based system comprising:
a first semiconductor layer comprising first alignment marks and first transistors, wherein said first transistors are interconnected by at least one metal layer comprising aluminum or copper;
a second mono-crystallized semiconductor layer comprising second transistors and overlaying said at least one metal layer, wherein said at least one metal layer is in-between said first semiconductor layer and said second mono-crystallized semiconductor layer; and
a reusable donor wafer,
wherein said second transistors comprise horizontally oriented transistors, and
wherein said second mono-crystallized semiconductor layer is transferred from said reusable donor wafer.
24. A system according to claim 23 wherein said second mono-crystallized semiconductor layer is less than about 150 nm in thickness.
25. A system according to claim 23 wherein said second transistors comprise a plurality of N-type transistors and P-type transistors.
26. A system according to claim 23 , further comprising:
a heat spreader between said first semiconductor layer and said second mono-crystallized semiconductor layer.
27. A system according to claim 23 ,
wherein said second mono-crystallized semiconductor layer further comprises a plurality of thermal contacts, and
wherein said thermal contacts are adapted to conduct heat but not electric current.
28. A system according to claim 23 , further comprising:
a plurality of connection paths between said second transistors and said first transistors,
wherein said plurality of connection paths comprise vias through said second mono-crystallized semiconductor layer, and
wherein at least one of said vias is less than about 150 nm in diameter.
29. A system according to claim 23 wherein at least one of said second transistors is one of:
(i) a recessed-channel transistor (RCAT);
(ii) a junction-less transistor;
(iii) a replacement-gate transistor;
(iv) a thin-side-up transistor; or
(v) a double gate transistor.
30. A system according to claim 23 , further comprising:
a plurality of connection paths between said second transistors and said first transistors,
wherein at least one of said connection paths has a contact to said second transistors, and
wherein said contact is also aligned to one of said first alignment marks.