Method for fabrication of a semiconductor device and structure

1. A method of manufacturing a semiconductor wafer, the method comprising:

providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks;

transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and

performing a lithography using at least one of said first alignment marks and at least one of said second alignment marks.

2. The method according to claim 1 wherein:

said monocrystalline layer further comprises transistors formed therein.

3. The method according to claim 1 wherein said transferring comprises:

performing layer transfer of said monocrystalline layer to a carrier; and

performing layer transfer of said monocrystalline layer on top of said metal layers from said carrier.

4. The method according to claim 1 , further comprising:

etching said monocrystalline layer to form a plurality of transistors.

5. The method according to claim 1 , further comprising:

performing gate replacement in said monocrystalline layer.

6. The method according to claim 1 , further comprising:

optical annealing of at least one region of said monocrystalline layer.

7. The method according to claim 2 , wherein:

said monocrystalline layer comprises a repeating pattern of said transistors.

8. A method of manufacturing a semiconductor wafer, the method comprising:

providing a base wafer comprising a semiconductor substrate, metal layers, and first alignment marks;

preparing a monocrystalline layer comprising semiconductor regions comprising transistors;

performing layer transfer of said monocrystalline layer on top of said metal layers; and

annealing at least one region of said monocrystalline layer.

9. The method according to claim 8 wherein said monocrystalline layer further comprises second alignment marks, the method further comprising:

performing a lithography using at least one of said first alignment marks and at least one of said second alignment marks.

10. The method according to claim 8 , wherein said layer transfer comprises:

performing layer transfer of said monocrystalline layer to a carrier; and

performing layer transfer of said monocrystalline layer on top of said metal layers from said carrier.

11. The method according to claim 10 wherein:

said annealing is subsequent to said performing layer transfer of said monocrystalline layer to said carrier.

12. The method according to claim 8 , wherein said annealing comprises optical annealing.

13. The method according to claim 8 , wherein

said transistors comprise p-type transistors and n-type transistors.

14. A method of manufacturing a semiconductor wafer, the method comprising:

providing a base wafer comprising a semiconductor substrate, metal layers, and first alignment marks;

preparing a monocrystalline layer comprising semiconductor regions;

performing layer transfer of said monocrystalline layer on top of said metal layers; and

etching said monocrystalline layer to define horizontally oriented transistors.

15. The method according to claim 14 , wherein said etching comprises etching gate locations.

16. The method according to claim 14 , wherein said monocrystalline layer comprises second alignment marks, and the method further comprising:

performing a lithography using at least one of said first alignment marks and at least one of said second alignment marks.

17. The method according to claim 14 , wherein said monocrystalline layer further comprises a repeating pattern of said transistors.

18. The method according to claim 14 , wherein said transistors comprise planar transistors.

19. The method according to claim 14 , wherein said transistors comprise p-type transistors and n-type transistors.

20. The method according to claim 14 , further comprising:

annealing of at least one of said semiconductor regions of said monocrystalline layer.

21. A method of manufacturing a semiconductor wafer, the method comprising:

providing a base wafer comprising a semiconductor substrate, metal layers, and first alignment marks;

preparing a first monocrystalline layer comprising semiconductor regions;

performing layer transfer of said first monocrystalline layer on top of said metal layers;

preparing a second monocrystalline layer comprising semiconductor regions;

performing layer transfer of said second monocrystalline layer on top of said first monocrystalline layer; and

processing second monocrystalline layer to define horizontally oriented transistors.

22. The method according to claim 21 , wherein said process further comprising etching step.

23. The method according to claim 21 , wherein;

said first monocrystalline layer comprises second alignment marks, and the method further comprising:

performing a lithography step using at least one of said first alignment marks and at least one of said second alignment marks.

24. The method according to claim 21 , wherein said horizontally oriented transistors comprise junction-less transistors.

25. The method according to claim 21 , wherein said horizontally oriented transistors comprise recessed channel transistors.

26. The method according to claim 21 , wherein said horizontally oriented transistors comprise p-type transistors and n-type transistors.

27. The method according to claim 21 , further comprising:

annealing at least one region of said monocrystalline layer.

28. The method according to claim 21 , wherein said processing comprises gate replacement.

29. The method according to claim 21 ,

wherein said first monocrystalline layer further comprises transistors,

wherein said transistors in said first monocrystalline layer are one of n-type transistors or p-type transistors, and

wherein said horizontally oriented transistors are the other of n-type transistors or p-type transistors.