Information processing apparatus
View Patent ↗A CPU ( 1 ) of an information processing apparatus ( 8 ) executes software stored in a DRAM ( 7 ). A watchdog timer ( 2 ) monitors the operation of the software. A hardware monitoring device ( 4 ) monitors the state of hardware provided in the information processing apparatus ( 8 ). Results of the monitoring are managed by a management LSI chip ( 3 ). A non-volatile memory ( 6 ) is where failure information is saved. If no watchdog toggles are received for a given period of time, the watchdog timer ( 2 ) notifies the CPU ( 1 ) with an NMI signal and starts the second round of time counting. The CPU ( 1 ) collects failure information from the management LSI ( 3 ). The CPU ( 1 ) is rebooted through cold reset when failure information collection is completed, and through hot reset when failure information collection is incomplete. In the case of hot reset, the CPU ( 1 ) collects failure information after rebooted.
1. An information processing apparatus comprising:
(a) a CPU which executes software necessary for the information processing apparatus to operate and which keeps outputting a monitoring notification to a monitor while the software is running;
(b) a management device which monitors states of hardware components built in the information processing apparatus other than the CPU, and which manages results of the monitoring as failure information;
(c) a memory device which saves the failure information managed by the management device; and
(d) a watchdog timer which serves as the monitor of the CPU and which starts an initial round of time counting for monitoring after booting to monitor operation of the CPU in executing the software, based on the monitoring notification received from the CPU, the watchdog timer being configured to:
(d-1) when receiving no monitoring notification in a given period of time during the monitoring of the CPU, notify the CPU with an interrupt signal and start counting time anew as a second round of time counting for monitoring so that the CPU notified with the interrupt signal starts a collection process in which the failure information is collected from the management device and the collected failure information is saved in the memory device;
(d-2) after the start of the collection process, when the monitoring notification which the watchdog timer is supposed to receive from the CPU stops because the CPU has completed the collection process and the management device accordingly has notified the CPU of the completion of collection, issue a first reset command to the CPU and the management device after a given period of time to reboot the CPU so that the rebooted CPU performs a first reset operation in which the failure information is not collected from the management device; and
(d-3) after the start of the collection process, when, as opposed to the issuing of the first reset command, the watchdog timer does not receive the monitoring notification from the CPU in the given period of time with the collection process by the CPU incomplete, issue a second reset command to the CPU and the management device to reboot the CPU so that the rebooted CPU performs a second reset operation in which the failure information collected from the management device is saved in the memory device.
2. An information processing apparatus according to claim 1 , wherein the management device monitors the states of the hardware components all the time and manages results of the monitoring all the time as failure information.
3. An information processing apparatus according to claim 1 ,
wherein, when there is no monitoring notification in the given period of time during the monitoring of the CPU, the watchdog timer notifies the CPU with a non-maskable interrupt signal, and
wherein, notified with the non-maskable interrupt signal, the CPU outputs anew the monitoring notification to the watchdog timer so that the watchdog timer starts the second round of time counting for monitoring.
4. An information processing apparatus according to claim 1 , wherein the management device comprises:
a hardware monitoring device which monitors states of hardware components built in the information processing apparatus; and
a management LSI chip which manages results of the monitoring by the hardware monitoring device.