DEFECT MAPPING FOR A DIGITAL DISPLAY
A digital display with image data storage memory that minimizes the impact of defective memory cells by remapping stored image data. Memory defects may be detected by automatic or visual testing. The digital display may perform a mapping process such that image data placed in the location of the defective storage cells is based on the significance of the data, both by bit and by color. The mapping process may operate on addressed rows of memory cells of the digital display.
1 . A digital display, comprising:
an array of pixels;
a memory buffer that stores image data for the pixels; and
memory addressing circuitry coupled to the memory buffer, the memory addressing circuitry operable to store relatively lower significant bits of the image data in locations within the memory buffer that have a defect therein.
2 . The digital display of claim 1 , wherein the display includes memory registers therein that indicate the locations within the memory buffer that have a defect.
3 . The digital display of claim 2 , wherein the memory addressing circuitry is operable to store image data for a less easily perceived color than green in portions of the memory buffer with defective cells.
4 . The digital display of claim 2 , wherein the memory buffer is tested to determine the locations within the memory buffer that have a defect therein and information indicative of those locations is stored in the memory registers.
5 . The digital display of claim 1 , wherein the polarity of the stored image data is selected to be such that a defect causes a pixel to provide less light than would be displayed by the pixel if there were no defect.
6 . The digital display of claim 1 , wherein image data bits of the image data are stored in independently addressable rows within the memory buffer, and wherein the memory addressing circuitry is operable to store relatively lower significant image data bits in rows within the memory buffer that have a defect therein.
7 . The digital display of claim 1 , further comprising programmable row select blocks, each programmable row select block associated with a group of co-addressed pixel rows of the array of pixels.
8 . The digital display of claim 7 , wherein the programmable row select blocks comprise cross-point switches.
9 . The digital display of claim 1 , wherein the memory addressing circuitry is operable to store the image data in locations of the memory buffer based on a ranking of image data bits of the image data according to their visual significance.
10 . The digital display of claim 9 , wherein memory registers for each row of pixels are scanned for defects, and wherein a first row having a defective register is assigned to the visually least significant bit according to the ranking.
11 . The digital display of claim 9 , wherein memory registers for each row of pixels are scanned for defects, and wherein a first row not having a defective register is assigned to the visually most significant bit according to the ranking.
12 . The digital display of claim 9 , wherein a least significant position in the ranking of image data bits of the image data is assigned to a least significant bit of blue image data.
13 . A method, comprising:
identifying locations within a memory buffer of a digital display that have one or more defects;
storing information indicative of which locations have the defects; and
using the stored information to place relatively lower significant bits of image data in the locations within the memory buffer that have defects.
14 . The method of claim 13 , further including selecting the polarity of the stored image data to be such that a defect causes a pixel to provide less light than would be displayed by the pixel if there were no defect.
15 . The method of claim 13 , wherein image data bits of the image data of equal significance are stored in logical groups of the memory buffer.
16 . The method of claim 15 , wherein the logical groups comprise rows of the memory buffer.
17 . The method of claim 13 , wherein the identifying step is performed by the digital display as a built-in self test.
18 . The method of claim 17 , wherein the digital display performs the built-in-self-test at power-on of the display.
19 . A method, comprising:
receiving image data at a digital display; and
storing the image data in a memory buffer of the digital display, wherein selection of an image data bit of the image data stored in a location of a known defective memory cell of the memory buffer is based on a visual significance of the image data bit.
20 . The method of claim 19 , wherein the selection of the image data bit of the image data is performed by a remapping of rows of the memory buffer.