IP Library Granted Patent US 8,487,395
Granted Patent B2
US 8,487,395 · App. 13/247,254 · Granted Jul 16, 2013

Thin-film transistor array device, el display panel, el display device, thin-film transistor array device manufacturing method, el display panel manufacturing method

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Quick Facts
Patent No.
US 8,487,395
App. No.
13/247,254
Granted
Jul 16, 2013
Kind
B2
Abstract

A thin-film transistor array device includes a passivation film above first and second bottom gate transistors. A gate wire is below the passivation film. A source wire and a relay wire are above the passivation film. The source wire is electrically connected to a source electrode of the first transistor via a first hole in the passivation film. A conductive oxide film is between the passivation film and both the source wire and the relay electrode and not electrically connected between the source wire and the relay electrode. The conductive oxide film covers an end portion of the gate wire that is exposed via a second hole in the passivation film. The conductive oxide film is between the relay electrode and a current-supply electrode of the second transistor and electrically connects the relay electrode and the current-supply electrode via a third hole in the passivation film.

Claims (120)

1. A thin-film transistor array device, the thin-film transistor array device being stacked with an electroluminescence layer, an interlayer insulating film between the electroluminescence layer and the thin-film transistor array device, the electroluminescent layer including electroluminescence light-emitting elements that each include a lower electrode, said thin-film transistor array device comprising:

a substrate;

a first transistor above the substrate and including a first transistor gate electrode and a first transistor source electrode;

a second transistor including a current-supply electrode for supplying current, the current-supply electrode being electrically connected to the lower electrode;

a passivation film between the interlayer insulating film and both the first transistor and the second transistor;

a gate wire above the substrate and below the passivation film in a first layer, the gate wire being electrically connected to the first transistor gate electrode;

a source wire transverse to the gate wire and above the passivation film in a second layer different than the first transistor source electrode, the source wire being electrically connected to the first transistor source electrode via a first hole in the passivation film;

a relay electrode above the passivation film in the second layer and overlapping with the current-supply electrode for being a relay between the current-supply electrode and the lower electrode; and

a conductive oxide film above the passivation film and between the passivation film and both the source wire and the relay electrode, the conductive oxide film being electrically disconnected between the source wire and the relay electrode,

wherein the first transistor and the second transistor are bottom gate transistors,

an end portion of the gate wire is exposed through the passivation film via a second hole in the passivation film, the end portion of the gate wire being connectible with a gate driving circuit that is outside the thin-film transistor array device,

the conductive oxide film covers the end portion of the gate wire that is exposed through the passivation film via the second hole,

the current-supply electrode is electrically connected to the lower electrode via a third hole in the passivation film,

the conductive oxide film is between the current-supply electrode and the relay electrode and electrically connects and the current-supply electrode and the relay electrode, and

the relay electrode comprises a same material as the source wire.

2. The thin-film transistor array device according to claim 1 ,

wherein the lower electrode comprises a metal primarily composed of aluminum.

3. The thin-film transistor array device according to claim 1 ,

wherein the source wire and the relay electrode each include a surface that is in contact with the conductive oxide film and comprises a metal that includes at least one of copper, molybdenum, titanium, and tungsten.

4. The thin-film transistor array device according to claim 1 ,

wherein the source wire and the relay electrode include a layered structure.

5. The thin-film transistor array device according to claim 1 ,

wherein the interlayer insulating film includes an organic film layer and an inorganic film layer, and

the inorganic film layer covers the source wire and the relay electrode.

6. The thin-film transistor array device according to claim 1 ,

wherein the first transistor and the second transistor each include a crystalline semiconductor layer, and

the first transistor gate electrode and a second transistor gate electrode included in the second transistor comprise a first metal having higher heat-resistance than a second metal of which the gate wire comprises.

7. The thin-film transistor array device according to claim 6 ,

wherein the first metal includes one of molybdenum, tungsten, titanium, tantalum, and nickel.

8. The thin-film transistor array device according to claim 1 ,

wherein the conductive oxide film comprises indium and one of tin and zinc.

9. The thin-film transistor array device according to claim 1 ,

wherein a relay wire is on a gate insulating film,

an end portion of the source wire is connected, via the conductive oxide film, to a first end portion of the relay wire,

a second end portion of the relay wire is exposed through a fourth hole in the passivation film and is connectable with a source driving circuit that is outside the thin-film transistor array device, and

the conductive oxide film covers the second end portion of the relay wire that is exposed through the fourth hole.

10. The thin-film transistor array device according to claim 9 ,

wherein the relay wire is in the first layer and comprises a same material as the gate wire.

11. The thin-film transistor array device according to claim 1 ,

wherein the conductive oxide layer is below the source wire and extends beyond an end of the source wire and is exposed, and

an exposed region of the conductive oxide layer is connectable with a source driving circuit that is outside the thin-film transistor array device.

12. The thin-film transistor array device according to claim 11 ,

wherein an elastic body is above a gate insulating film and overlaps with at least a portion of the exposed region of the conductive oxide film that is connectable with the gate driving circuit.

13. The thin-film transistor array device according to claim 1 ,

wherein the elastic body is in the first layer and comprises a same material as the gate wire.

14. An electroluminescence display panel, comprising:

an upper electrode;

a lower electrode;

an electroluminescence layer including an electroluminescence light-emitting element that includes a light-emitting function layer between the upper electrode and the lower electrode;

a thin-film transistor array device for controlling the electroluminescence light-emitting element; and

an interlayer insulating film between the electroluminescence layer and the thin-film transistor array device,

wherein the lower electrode is electrically connected to the thin-film transistor array device via a contact hole in the interlayer insulating film,

the thin-film transistor array device includes:

a substrate;

a first transistor above the substrate and including a first transistor gate electrode and a first transistor source electrode;

a second transistor including a current-supply electrode for supplying current, the current-supply electrode being electrically connected to the lower electrode;

a passivation film between the interlayer insulating film and both the first transistor and the second transistor;

a gate wire above the substrate and below the passivation film in a first layer, the gate wire being electrically connected to the first transistor gate electrode;

a source wire transverse to the gate wire and above the passivation film in a second layer different than the first transistor source electrode, the source wire being electrically connected to the first transistor source electrode via a first hole in the passivation film;

a relay electrode above the passivation film in the second layer and overlapping with the current-supply electrode for being a relay between the current-supply electrode and the lower electrode; and

a conductive oxide film above the passivation film and between the passivation film and both the source wire and the relay electrode, the conductive oxide film being electrically disconnected between the source wire and the relay electrode,

wherein the first transistor and the second transistor are bottom gate transistors,

an end portion of the gate wire is exposed through the passivation film via a second hole in the passivation film, the end portion of the gate wire being connectible with a gate driving circuit that is outside the thin-film transistor array device,

the conductive oxide film covers the end portion of the gate wire that is exposed through the passivation film via the second hole,

the current-supply electrode is electrically connected to the lower electrode via a third hole in the passivation film and the contact hole in the interlayer insulating film,

the conductive oxide film is between the current-supply electrode and the relay electrode and electrically connects the current-supply electrode and the relay electrode, and

the relay electrode comprises a same material as the source wire.

15. The electroluminescence display panel according to claim 14 ,

wherein the lower electrode comprises a metal primarily composed of aluminum.

16. The electroluminescence display panel according to claim 14 ,

wherein the lower electrode and the relay electrode are connected in a flat region extending along a circumference of an upper part of a fourth hole in the passivation film.

17. An electroluminescence display device comprising the electroluminescence display panel according to claim 14 .

18. A method of manufacturing a thin-film transistor array device, comprising:

preparing a substrate;

forming a gate wire above the substrate;

forming a first transistor including a first transistor gate electrode and a first transistor source electrode above the substrate;

forming a second transistor including a current-supply electrode above the substrate for supplying current;

forming a passivation film above the first transistor and the second transistor;

forming a conductive oxide film above the passivation film;

forming a source wire above the gate wire and transverse to the gate wire; and

forming a relay electrode above the passivation film that overlaps with the current-supply electrode, the relay electrode being a relay between the current-supply electrode and the lower electrode,

wherein the first transistor and the second transistor are bottom gate transistors,

the gate wire is electrically connected to the first transistor gate electrode and below the passivation film in a first layer,

the source wire is above the passivation film in a second layer different than the first transistor source electrode and electrically connected to the first transistor source electrode via a first hole in the passivation film,

after forming the passivation film and before forming the conductive oxide film above the passivation film, an end portion of the gate wire is exposed through the passivation film via a second hole in the passivation film, the end portion of the gate wire being formed into a terminal for connection with a gate driving circuit that is outside the thin-film transistor array device,

the conductive oxide film is formed to cover the end portion of the gate wire that is exposed through the passivation film via the second hole,

the conductive oxide film is formed between the passivation film and both the source wire and the relay electrode and divided between the source wire and the relay electrode,

the conductive oxide film is between the relay electrode and the current-supply electrode and electrically connects the relay electrode and the current-supply electrode, and

the relay electrode is formed in the second layer and comprises a same material as the source wire.

19. The method of manufacturing a thin-film transistor array device according to claim 18 ,

wherein the lower electrode comprises a metal primarily composed of aluminum.

20. The method of manufacturing a thin-film transistor array device according to claim 18 ,

wherein the source wire and the relay electrode each include a surface that is in contact with the conductive oxide film and comprises a metal that includes at least one of copper, molybdenum, titanium, and tungsten.

21. The method of manufacturing a thin-film transistor array device according to claim 18 ,

wherein the first transistor and the second transistor each include a crystalline semiconductor layer, and

the first transistor gate electrode and a second transistor gate electrode included in the second transistor comprise a first metal having a higher heat-resistance than a second metal of which the gate wire comprises.

22. The method of manufacturing a thin-film transistor array device according to claim 18 ,

wherein the conductive oxide film comprises indium and one of tin and zinc.

23. A method of manufacturing an electroluminescence panel, comprising:

preparing a substrate;

forming a gate wire above the substrate;

forming a first transistor including a first transistor gate electrode and a first transistor source electrode above the substrate;

forming a second transistor including a current-supply electrode above the substrate for supplying current;

forming a passivation film above the first transistor and the second transistor;

forming a conductive oxide film above the passivation film;

forming a source wire above the gate wire and transverse to the gate wire;

forming a relay electrode above the passivation film that overlaps with the current-supply electrode, the relay electrode being a relay between the current-supply electrode and the lower electrode;

forming an interlayer insulating film above the passivation film;

forming a lower electrode above the interlayer insulating film;

forming a light-emitting function layer above the lower electrode; and

forming an upper electrode above the light-emitting function layer,

wherein the first transistor and the second transistor are bottom gate transistors,

the gate wire is electrically connected to the first transistor gate electrode and below the passivation film in a first layer,

the source wire is above the passivation film in a second layer different than the first transistor source electrode and electrically connected to the first transistor source electrode via a first hole in the passivation film,

the lower electrode is electrically connected to a thin-film transistor array device via a second hole in the passivation film and a contact hole in the interlayer insulating film,

after forming the passivation film and before forming the conductive oxide film above the passivation film, an end portion of the gate wire is exposed through the passivation film via a third hole in the passivation film, the end portion of the gate wire being formed into a terminal for connection with a gate driving circuit that is outside the thin-film transistor array device,

the conductive oxide film is formed to cover the end portion of the gate wire that is exposed through the passivation film via the third hole,

the conductive oxide film is formed between the passivation film and both the source wire and the relay electrode and divided between the source wire and the relay electrode,

the conductive oxide film is between the relay electrode and the current-supply electrode and electrically connects the relay electrode and the current-supply electrode, and

the relay electrode is formed in the second layer and comprises a same material as the source wire.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2019
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
To: JOLED INC.
Reel/Frame 049404/0183 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2015
From: PANASONIC CORPORATION
To: JOLED INC
Reel/Frame 035145/0100 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2011
From: KANEGAE, ARINOBU; KAWACHI, GENSHIRO
To: PANASONIC CORPORATION; PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 027218/0471 →