IP Library Granted Patent US 8,487,909
Granted Patent B2
US 8,487,909 · App. 13/247,550 · Granted Jul 16, 2013

Method and apparatus for parallel scanning and data processing for touch sense arrays

Inventors: Andriy Yarosh (Moguliv-Podilskiy, UA); Roman Ogirko (Lviv, UA); Oleksandr Pirogov (Lviv, UA); Viktor Kremin (Lviv, UA); Roman Sharamaga (Lviv, UA); Anton Konovalov (Khmelnitsky, UA); Andriy Maharyta (Lviv, UA); Haneef Mohammed (Beaverton, OR)
Assignee: Cypress Semiconductor Corporation
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Quick Facts
Patent No.
US 8,487,909
App. No.
13/247,550
Granted
Jul 16, 2013
Kind
B2
Abstract

A parallel pipelining method of operation of a touch sense controller for processing data into a touch map is disclosed. A current full scan of response signals to at least one excitation of a touch sense array is received using a first thread of a processing device. The current full scan of response signals is processed using a second thread of the processing device to render a touch map corresponding to the touch sense array. A next full scan of response signals is received using the first thread. Receiving the next full scan and processing the current full scan are performed substantially simultaneously.

Claims (33)

1. A method, comprising:

receiving a current full scan of response signals to at least one excitation of a touch sense array using a first thread of a processing device;

processing the current full scan of response signals using a second thread of the processing device to render a touch map corresponding to the touch sense array; and

receiving a next full scan of response signals using the first thread,

wherein the receiving the next full scan and processing the current full scan are performed substantially simultaneously.

2. The method of claim 1 , wherein the first thread is a hardware scan thread of a sequencer and is not part of a central processing unit (CPU) of the processing device.

3. The method of claim 1 , wherein the second thread is a hardware thread of a digital filter block (DFB) and is not part of a CPU of the processing device.

4. The method of claim 3 , further comprising storing data corresponding to individual slots of response signals of the current or next full scan of response signals in corresponding single buffers.

5. The method of claim 4 , further comprising combining the single buffers into a full sense array raw data buffer in order of slots.

6. The method of claim 5 , further comprising directly transferring the combined data in the full sense array raw data buffer to memory using direct memory access (DMA).

7. The method of claim 1 , wherein the second thread is a software thread of a CPU of the processing device.

8. The method of claim 7 , wherein the first thread and the second thread are coordinated using semaphores or interrupts.

9. The method of claim 1 , wherein processing the current full scan is initiated in response to receiving an interrupt corresponding to completion of receiving the current full scan.

10. The method of claim 1 , wherein receiving the next full scan is initiated in response to receiving an interrupt corresponding to completion of processing of the current full scan.

11. A circuit, comprising:

a sequencer configured to receive a current full scan of response signals to at least one excitation of a touch sense array using a first thread and configured to receive a next full scan of response signals using the first thread; and

processing logic configured to process the current full scan of response signals using a second thread to render a touch map corresponding to the touch sense array,

wherein receiving the next full scan and processing the current full scan are performed substantially simultaneously.

12. The circuit of claim 11 , wherein the first thread is a hardware scan thread of the sequencer and is not part of a central processing unit (CPU).

13. The circuit of claim 11 , wherein the second thread is a hardware thread of a digital filter block (DFB) and is not part of a CPU.

14. The circuit of claim 11 , wherein the second thread is a software thread of a CPU.

15. The circuit of claim 11 , further comprising a CPU is configured to initiate processing the current full scan in response to an interrupt corresponding to completion of receiving the current full scan from the sequencer.

16. The circuit of claim 11 , further comprising a CPU configured to initiate processing the next full scan in response to an interrupt corresponding to completion of receiving the current full scan from the sequencer.

17. The circuit of claim 11 , further comprising:

a memory;

a direct memory access (DMA) controller coupled to the memory and the sequencer, wherein the DMA controller is configured to transfer data corresponding to individual response signals of the current or next full scan of response signals to corresponding single buffers in the memory.

18. The circuit of claim 17 , wherein the DMA controller is further configured to combine the single buffers into a full sense array raw data buffer in order of slots in the memory.

19. An apparatus, comprising:

a processing device configured to detect a conductive object proximate to a touch sense array, wherein the processing device comprises:

a sequencer configured to receive a current full scan of response signals to at least excitation of a touch sense array using a first thread and configured to receive a next full scan of response signals using the first thread; and

processing logic configured to process the current full scan of response signals using a second thread to render a touch map corresponding to the touch sense array,

wherein receiving the next full scan and processing the current full scan are performed substantially simultaneously.

20. The apparatus of claim 19 , wherein the second thread is a hardware thread of a DFB and is not part of a CPU of the processing device.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2013
From: MAHARYTA, ANDRIY; MOHAMMED, HANEEF
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 030635/0603 →
PATENT SECURITY AGREEMENT Recorded Aug 28, 2012
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 028863/0870 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2011
From: YAROSH, ANDRIY; OGIRKO, ROMAN; PIROGOV, OLEKSANDR; KREMIN, VIKTOR; SHARAMAGA, ROMAN; KONOVALOV, ANTON
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 027010/0709 →
Continuity (2)
Provisional Application 61512358 · Jul 27, 2011
Related Publication 20130027346A1 · Jan 31, 2013