IP Library Granted Patent US 8,575,993
Granted Patent B2
US 8,575,993 · App. 13/247,694 · Granted Nov 5, 2013

Integrated circuit with pre-heating for reduced subthreshold leakage

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Quick Facts
Patent No.
US 8,575,993
App. No.
13/247,694
Granted
Nov 5, 2013
Kind
B2
Abstract

Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by “pre-heating” the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given, minimum temperature at which the IC is designed (or guaranteed) to properly function at are provided.

Claims (43)

1. A system comprising:

a first device configured to form an inversion layer at a first threshold voltage to allow the flow of electrical current through the first device;

a variable frequency oscillator configured to provide a clock signal;

a storage element configured to store a logic value, produced at least in part by the first device, upon occurrence of a transition in the clock signal; and

a pre-heating controller configured to set a frequency of the clock signal to a first frequency if a temperature associated with the first device is determined to be below a particular temperature and to a second frequency if the temperature associated with the first device is determined to be above the particular temperature, wherein the first frequency is less than the second frequency.

2. The system of claim 1 , further comprising:

a second device configured to form an inversion layer at a second threshold voltage to allow the flow of electrical current through the second device, wherein the second threshold voltage is less than the first threshold voltage.

3. The system of claim 2 , wherein the logic value is further produced in part by the second device.

4. The system of claim 1 , further comprising:

a temperature sensor configured to sense the temperature associated with the first device.

5. The system of claim 4 , wherein the pre-heating controller is configured to determine whether the temperature associated with the first device is below or above the particular temperature based on the temperature associated with the first device sensed by the temperature sensor.

6. The system of claim 1 , wherein the pre-heating controller is configured to determine whether the temperature associated with the first device is below or above the particular temperature based on a number of clock cycles of the clock signal that have elapsed.

7. The system of claim 1 , wherein the pre-heating controller is configured to determine whether the temperature associated with the first device is below or above the particular temperature based on an amount of energy consumed by one or more logic blocks associated with the first device.

8. The system of claim 1 , wherein the storage element is a flip-flop or a latch.

9. The system of claim 1 , where the first device is a transistor.

10. A method comprising:

providing a clock signal;

storing a logic value in a storage element upon occurrence of a transition in the clock signal, the logic value produced at least in part by a first device configured to form an inversion layer at a first threshold voltage to allow the flow of electrical current through the first device; and

setting a frequency of the clock signal to a first frequency if a temperature associated with the first device is determined to be below a particular temperature and to a second frequency if the temperature associated with the first device is determined to be above the particular temperature, wherein the first frequency is less than the second frequency.

11. The method of claim 10 , further comprising:

sensing the temperature associated with the first device using a temperature sensor.

12. The method of claim 11 , further comprising:

determining whether the temperature associated with the first device is below or above the particular temperature based on the temperature associated with the first device sensed by the temperature sensor.

13. The method of claim 10 , further comprising:

determining whether the temperature associated with the first device is below or above the particular temperature based on a number of clock cycles of the clock signal that have elapsed.

14. The method of claim 10 , further comprising:

determining whether the temperature associated with the first device is below or above the particular temperature based on an amount of energy consumed by one or more logic blocks associated with the first device.

15. A system comprising:

a first device configured to form an inversion layer at a first threshold voltage to allow the flow of electrical current through the first device;

a second device configured to form an inversion layer at a second threshold voltage to allow the flow of electrical current through the second device, wherein the second threshold voltage is less than the first threshold voltage;

a sequential storage element configured to store a logic value, produced at least in part by the first device and the second device, upon occurrence of a transition in a clock signal;

a voltage converter configured to provide a supply voltage to the first device;

a pre-heating controller configured to set the supply voltage to a first voltage if a temperature associated with the first device is determined to be below a particular temperature and to a second voltage if the temperature associated with the first device is determined to be above the particular temperature, wherein the first voltage is greater than the second voltage.

16. The system of claim 15 , further comprising:

a temperature sensor configured to sense the temperature associated with the first device.

17. The system of claim 16 , wherein the pre-heating controller is configured to determine whether the temperature associated with the first device is below or above the particular temperature based on the temperature associated with the first device sensed by the temperature sensor.

18. The system of claim 15 , wherein the pre-heating controller is configured to determine whether the temperature associated with the first device is below or above the particular temperature based on a number of clock cycles of the clock signal that have elapsed.

19. The system of claim 15 , wherein the pre-heating controller is configured to determine whether the temperature associated with the first device is below or above the particular temperature based on an amount of energy consumed by one or more logic blocks associated with the first device.

20. A system comprising:

a sequential logic block configured to process and provide output data, the sequential logic block including a first device configured to form an inversion layer at a first threshold voltage to allow the flow of electrical current through the first device;

a heating block configured to pre-heat the sequential logic block; and

a pre-heating controller configured to run the heating block and delay running the sequential logic block if a temperature associated with the sequential logic block is determined to be below a particular temperature, and to run the sequential logic block if the temperature associated with the sequential logic block is determined to be above the particular temperature.

21. The system of claim 20 , wherein the heating block includes a ring oscillator.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2011
From: PENZES, PAUL; FULLERTON, MARK
To: BROADCOM CORPORATION
Reel/Frame 026985/0444 →