Electronic module metalization system, apparatus, and methods of forming same
View Patent ↗Embodiments of electronic module metallization systems and apparatus and methods for forming same are described generally herein. Other embodiments may be described and claimed.
1. A semiconductor device, including:
a first channel having a length, the first channel tapered along its length;
a second channel having a length;
a third channel between and adjacent to the first and second channels;
a first metallization on the first channel, the first metallization having a length, a proximal end, and a distal end, the first metallization length greater than half the length of the first channel and the first metallization distal end width less than its proximal end width; and
a second metallization on the second channel, the second metallization having a length, a proximal end, and a distal end, the second metallization length greater than half the length of the second channel and the second metallization distal end width less than its proximal end width.
2. The semiconductor device of claim 1 , wherein the semiconductor device is a FET, the first channel is one of a source and drain, the second channel is the other of a drain and source, and the third channel is a gate.
3. The semiconductor device of claim 1 , wherein the first metallization is tapered along its length.
4. The semiconductor device of claim 3 , wherein the second metallization is tapered along its length.
5. The semiconductor device of claim 1 , further comprising a third metallization overlaying a portion of the first metallization, the third metallization having a length, a proximal end, and a distal end, wherein the third metallization length is less than the length of the first metallization and the third metallization distal end width is less than its proximal end width.
6. The semiconductor device of claim 1 , wherein the second channel is tapered along its length.
7. The semiconductor device comprising:
a first channel having a length;
a second channel having a length;
a third channel between and adjacent to the first and second channels;
a first metallization on the first channel, the first metallization having a length, a proximal end, and a distal end, the first metallization length greater than half the length of the first channel and the first metallization distal end width less than its proximal end width;
a second metallization on the second channel, the second metallization having a length, a proximal end, and a distal end, the second metallization length greater than half the length of the second channel and the second metallization distal end width less than its proximal end width; and
a third metallization overlaying a portion of the first metallization, the third metallization having a length, a proximal end, and a distal end, the third metallization length is less than the length of the first metallization and the third metallization distal end width is less than its proximal end width.
8. The semiconductor device of claim 7 , further comprising a fourth metallization overlaying a portion of the second metallization, the fourth metallization having a length, a proximal end, and a distal end, the fourth metallization length is less than the length of the second metallization and the fourth metallization distal end width is less than its proximal end width.
9. A semiconductor device, including:
a first channel having a length;
a second channel having a length;
a third channel between and adjacent to the first and second channels;
a first metallization on the first channel, the first metallization having a length, a proximal end, and a distal end, the first metallization length greater than half the length of the first channel;
a second metallization on the second channel, the second metallization having a length, a proximal end, and a distal end, the second metallization length greater than half the length of the second channel;
a third metallization overlaying a portion of the first metallization, the third metallization having a length, a proximal end, and a distal end, the third metallization length less than the length of the first metallization; and
a fourth metallization overlaying a portion of the second metallization, the fourth metallization having a length, a proximal end, and a distal end, the fourth metallization length less than the length of the second metallization.
10. The semiconductor device of claim 9 , wherein the first metallization distal end width is less than its proximal end width and the second metallization distal end width is less than its proximal end width.
11. The semiconductor device of claim 10 , wherein the third metallization distal end width is less than its proximal end width and the fourth metallization distal end width is less than its proximal end width.
12. The semiconductor device of claim 9 , wherein the semiconductor device is a FET, the first channel is one of a source and drain, the second channel is the other of a drain and source, and the third channel is a gate.
13. The semiconductor device of claim 12 , wherein the first metallization and the third metallization are tapered along their length.
14. The semiconductor device of claim 13 , wherein the second metallization and the fourth metallization are tapered along their length.
15. The semiconductor device of claim 14 , wherein the first channel and the second channel are tapered along their length.
16. The semiconductor device of claim 5 , further comprising a fourth metallization overlaying a portion of the second metallization, the fourth metallization having a length, proximal end, and distal end, the fourth metallization length is less than the length of the second metallization and the fourth metallization distal end width is less than its proximal end width.
17. A field effect transistor (FET) structure, including:
a source region, the source region tapered along its length;
a drain region;
a source metallization, the source metallization having a length, a proximal end, and a distal end, the source metallization length greater than half the length of the source region and the source metallization distal end width less than its proximal end width; and
a drain metallization, the drain metallization having a length, a proximal end, and a distal end, the drain metallization length greater than half the length of the drain region and the drain metallization distal end width less than its proximal end width.
18. The FET structure of claim 17 , wherein the source metallization is tapered along its length.
19. The FET structure of claim 18 , wherein the drain metallization is tapered along its length.
20. The FET structure of claim 17 , wherein the drain region is tapered along its length.
21. The FET structure of claim 17 , further comprising a second source metallization overlaying a portion of the source metallization, the second source metallization having a length, a proximal end, and a distal end, the second source metallization length is less than the length of the source metallization and the second source metallization distal end width is less than its proximal end width.
22. The FET structure of claim 21 , further comprising a second drain metallization overlaying a portion of the drain metallization, the second drain metallization having a length, a proximal end, and a distal end, the second drain metallization length less than the length of the drain metallization and the second drain metallization distal end width is less than its proximal end width.