Method and bus system for equalizing data information traffic and decoder

1. A method for equalizing data information traffic, comprising:

receiving data information sent by a device;

decoding the data information by decoding a bit value in a first designated bit position in the data information, wherein the data information carries a device ID, and the first designated bit position occupies at least one bit position in the device ID;

allocating at least two transmission interfaces for the data information according to a decoding result;

determining whether the data information traffic of the at least two transmission interfaces is balanced after the allocating; and

when the data information traffic of the at least two transmission interfaces is not balanced, switching the first designated bit position to a second designated bit position, and decoding a bit value on the second designated bit position, so as to balance the traffic of the at least two transmission interfaces by allocating the at least two transmission interfaces using at least a second decoding result of the second designated bit position after the switching.

2. The method according to claim 1 , before the allocating the transmission interfaces for the data information according to the decoding result of decoding the bit value on the first designated bit position in the data information, further comprising:

writing a device ID of a master device that initiates transmission of the data information into an address bit of the data information, so as to obtain an extended address bit.

3. The method according to claim 2 , wherein the transmission interface is an Advanced Extensible Interface (AXI), and when the number of the AXI interfaces is greater than two, the width of an internal data stream number of the master device is the integral part of Log 2N, wherein N is the number of the transmission interfaces.

4. The method according to claim 1 , wherein the determining whether the data information traffic of the at least two transmission interfaces is balanced comprises:

monitoring the data information traffic of the at least two transmission interfaces according to a depth of outstanding transmission of the at least two transmission interfaces; and

determining a magnitude relation of a depth difference between outstanding transmission of any two transmission interfaces in the at least two transmission interfaces and a preset threshold, and if the depth difference is greater than the preset threshold, the data information traffic of the transmission interfaces is not balanced; if the depth difference is less than the preset threshold, the data information traffic of the transmission interfaces is balanced; and if the depth difference is equal to the preset threshold, the data information traffic of the transmission interfaces is balanced or not balanced.

5. The method according to claim 4 , wherein the switching the designated bit position comprises:

generating statistics on a plurality of designated bit values located at the same designated bit position of the device IDs in each data information in the transmission interface with the largest outstanding transmission depth in the at least two transmission interfaces, and switching the designated bit position to a position with the smallest difference between the number of 0s and the number of 1s at the designated bit position of each device ID.

6. The method according to claim 1 , wherein the device ID comprises a device number and an internal data stream number of a device.

7. A method for equalizing data information traffic, comprising:

decoding a bit value on a first designated bit position in data information, and sending decoding results to a bus system, so that the bus system allocates transmission interfaces for the data information according to the decoding result; and

when the data information traffic of the transmission interfaces of the bus system is not balanced, switching the first designated bit position to a second designated bit position under the control of the bus system, and decoding a bit value on the second designated bit position after switching to determine a second decoding result, so as to balance the data information traffic of the transmission interfaces by allocating the transmission interfaces and to further balance the data information traffic of the transmission interfaces using at least the second decoding result of the second designated bit position after the switching.

8. A bus system for equalizing data information traffic, comprising:

an interface allocation module, configured to decode the data information by decoding a bit value in a first designated bit position in the data information, wherein the data information carries a device ID, and the first designated bit position occupies at least one bit position in the device ID, and allocate transmission interfaces for data information according to the decoding;

a traffic judging module, configured to determine whether the data information traffic of the transmission interfaces is balanced after the allocating; and

a bit position switching module, configured to switch the designated bit position when the data information traffic of the transmission interfaces is not balanced, and decode a bit value on the designated bit position after switching, so as to balance the traffic of the transmission interfaces by allocating the transmission interfaces using a result of the decoding of the designated bit position after the switching.

9. The bus system according to claim 8 , wherein the bus system is an Advanced Extensible Interface (AXI) system, and further comprises:

an address extension module, configured to write a device ID of a master device that initiates transmission into an address bit of the data information, so as to obtain an extended address bit.

10. The bus system according to claim 8 , wherein the traffic judging module comprises:

a traffic monitoring unit, configured to monitor the data information traffic of the transmission interfaces according to a depth of outstanding transmission of the transmission interfaces; and

a traffic judging unit, configured to determine a magnitude relation of a depth difference between outstanding transmission of any two transmission interfaces in the transmission interfaces and a preset threshold, and if the depth difference is greater than the preset threshold, the data information traffic of the transmission interfaces is not balanced; if the depth difference is less than the preset threshold, the data information traffic of the transmission interfaces is balanced; and if the depth difference is equal to the preset threshold, the data information traffic of the transmission interfaces is balanced or not balanced.

11. The bus system according to claim 8 , wherein the bit position switching module comprises:

a bit statistics unit, configured to generate statistics on a plurality of bit values located at the same position of the device IDs in each data information in the transmission interface with the largest outstanding transmission depth; and

a bit position switching unit, configured to switch the designated bit position to a position with the smallest difference between the number of 0s and the number of 1s at the designated bit position of each device ID.

12. The bus system according to claim 8 , wherein when the number of the transmission interfaces is greater than two, the width of an internal data stream number of the master device is Log 2N, wherein N is the number of the transmission interfaces.

13. A decoder, comprising:

a decoding module, configured to decode a bit value on a designated bit at a first designated bit location in data information, and send a decoding result to a bus system, so that the bus system allocates transmission interfaces for the data information according to the decoding result; and

a designated bit position switching module, configured to switch the designated bit position to a second designated bit location under the control of the bus system when the data information traffic of the transmission interfaces of the bus system is not balanced, so that the decoding module decodes a bit value on the second designated bit position after switching, so as to balance the traffic of the transmission interfaces by allocating the transmission interfaces using at least a second decoding result of the second designated bit position after the switching.