IP Library Granted Patent US 8,479,086
Granted Patent B2
US 8,479,086 · App. 13/251,340 · Granted Jul 2, 2013

Systems and methods for efficient parameter modification

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Quick Facts
Patent No.
US 8,479,086
App. No.
13/251,340
Granted
Jul 2, 2013
Kind
B2
Abstract

Various embodiments of the present invention provide systems and methods for data processing.

Claims (57)

1. A data processing system, the data processing system comprising:

a data detector circuit operable to apply a data detection algorithm to a first data set guided by a decoded output to yield a detected output;

a data decoder circuit operable to apply a data decode algorithm to a second data set to yield the decoded output, wherein the second data set is derived from the first data set;

a reliability monitor circuit operable to calculate an error rate based at least in part on an output selected from a group consisting of: a third data set derived from the decoded output, and the first data set;

a parameter modification control circuit operable to:

select a first value for a parameter and to store a first instance of the error rate corresponding to the first value;

select a second value for the parameter and to store a second instance of error count corresponding to the second value, wherein selecting the second value includes: determining a search direction based at least in part on the first value; and using the search direction and a step size to calculate the second value; and

select one of the first value and the second value based at least in part on a comparison of the first instance of the error rate and the second instance of the error rate.

2. The data processing system of claim 1 , wherein calculating the error rate includes comparing the third data set against a known data set.

3. The data processing system of claim 2 , wherein the third data set is a set of hard decision outputs.

4. The data processing system of claim 1 , wherein the data detection algorithm is selected from a group consisting of: a maximum a posteriori data detection algorithm and a Viterbi detection algorithm.

5. The data processing system of claim 3 , wherein the data decode algorithm is a low density parity check algorithm.

6. The data processing system of claim 1 , wherein the output is the third data set derived from the decoded output, and wherein the reliability monitor circuit comprises:

a comparator circuit operable to compare instances of the third data set against a known data set; and

a counter circuit operable to increment when an instance of the third data set is not equal to a corresponding instance of the known data set to yield the error rate.

7. The data processing circuit of claim 1 , wherein the output is the first data set, wherein the first data set includes soft data, and wherein the reliability monitor circuit comprises:

a comparator circuit operable to compare instances of the soft data against a threshold value; and

a counter circuit operable to increment when an instance of the soft data is less than the threshold value to yield the error rate.

8. The data processing system of claim 7 , wherein the threshold value is programmable.

9. The data processing system of claim 1 , wherein the steps size is programmable.

10. The data processing circuit of claim 1 , wherein the data processing system is implemented as part of a device selected from a group consisting of: a storage device and a receiving device.

11. The data processing system of claim 1 , wherein the data processing system is implemented as part of an integrated circuit.

12. A method for data processing, the method comprising:

performing a data detection algorithm using a data detector circuit on a first data set to yield a detected output;

performing a data decode algorithm using a data decoder circuit on a second data set derived from the first data set to yield a decoded output;

calculating an error rate based at least in part on an output selected from a group consisting of: a third data set derived from the decoded output, and the first data set;

selecting a first value for a parameter and storing a first instance of the error rate corresponding to the first value;

selecting a second value for the parameter and storing a second instance of error count corresponding to the second value, wherein selecting the second value includes: determining a search direction based at least in part on the first value; and using the search direction and a step size to calculate the second value; and

selecting one of the first value and the second value based at least in part on a comparison of the first instance of the error rate and the second instance of the error rate.

13. The method of claim 12 , wherein the output is the third data set derived from the decoded output, and wherein calculating the error rate comprises:

comparing instances of the third data set against a known data set; and

counting the number of instances of the third data set that are not equal to a corresponding instance of the known data set to yield the error rate.

14. The method of claim 12 , wherein the output is the first data set, wherein the first data set includes soft data, and wherein calculating the error rate comprises:

comparing instances of the soft data against a threshold value; and

counting the number of instances of the soft data that are less than the threshold value to yield the error rate.

15. The method of claim 14 , wherein the threshold value is programmable.

16. The method of claim 12 , wherein the third data set is a set of hard decision outputs.

17. The method of claim 12 , wherein the steps size is programmable.

18. A storage device, the storage device comprising:

a storage medium;

a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to information on the storage medium;

a read channel circuit including:

an analog to digital converter circuit operable to sample an analog signal derived from the sensed signal to yield a series of digital samples;

an equalizer circuit operable to equalize the digital samples to yield a first data set;

a data detector circuit operable to apply a data detection algorithm to the first data set;

a data decoder circuit operable to apply a data decode algorithm to a second data set to yield a decoded output, wherein the second data set is derived from the first data set;

a reliability monitor circuit operable to calculate an error rate based at least in part on an output selected from a group consisting of: a third data set derived from the decoded output, and the first data set;

a parameter modification control circuit operable to:

select a first value for a parameter and to store a first instance of the error rate corresponding to the first value;

select a second value for the parameter and to store a second instance of error count corresponding to the second value, wherein selecting the second value includes: determining a search direction based at least in part on the first value; and using the search direction and a step size to calculate the second value; and

select one of the first value and the second value based at least in part on a comparison of the first instance of the error rate and the second instance of the error rate.

19. The storage device of claim 18 , wherein the output is the third data set derived from the decoded output, and wherein the reliability monitor circuit comprises:

a comparator circuit operable to compare instances of the third data set against a known data set; and

a counter circuit operable to increment when an instance of the third data set is not equal to a corresponding instance of the known data set to yield the error rate.

20. The storage device of claim 18 , wherein the output is the first data set, wherein the first data set includes soft data, and wherein the reliability monitor circuit comprises:

a comparator circuit operable to compare instances of the soft data against a threshold value; and

a counter circuit operable to increment when an instance of the soft data is less than the threshold value to yield the error rate.

Assignments (10)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2011
From: XIA, HAITAO; HALL, KENNETH M.; LANDRETH, MARK A.; YANG, SHAOHUA
To: LSI CORPORATION
Reel/Frame 027143/0693 →