IP Library Granted Patent US 8,694,754
Granted Patent B2
US 8,694,754 · App. 13/251,491 · Granted Apr 8, 2014

Non-volatile memory-based mass storage devices and methods for writing data thereto

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,694,754
App. No.
13/251,491
Granted
Apr 8, 2014
Kind
B2
Abstract

A non-volatile solid state memory-based mass storage device having at least one non-volatile memory component and methods of operating the storage device. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.

Claims (19)

1. A NAND flash-based mass storage device, the storage device comprising:

a substrate;

at least two NAND flash memory components on the substrate, the memory components defining a NAND flash memory space organized into blocks and pages, each block having a block information record storing the number of program and erase cycles of the block;

a NAND flash controller including a flash translation layer, the flash translation layer translating logical block addresses into physical block addresses; and

an interface that interfaces the storage device with a host system through a system interface;

wherein the storage device sends the block information record of at least some blocks to the host, the host stores the block information record of the program and erase cycles in a content addressable memory, the content addressable memory associates the logical address of the block with the number of program and erase cycles and the flash translation layer translating the logical address to a physical block address, and, on writing data to the storage device, the host selects a number of program and erase cycles to obtain a logical block address from the content addressable memory the file translation layer translating the logical address into a physical address of a block to which the data are written.

2. The storage device of claim 1 , wherein the content addressable memory is a ternary content addressable memory.

3. The storage device of claim 1 , wherein the content addressable memory is a look-up table.

4. The storage device of claim 1 , wherein the content addressable memory is a translation lookaside buffer.

5. The storage device of claim 1 , wherein the interface conforms to the SATA standard.

6. The storage device of claim 1 , wherein the interface is a multi-lane PCIe interface.

7. The storage device of claim 1 , wherein the interface comprises at least two independent links connected to a multi-ported flash translation layer that acts as crossbar switch for addressing blocks in a unified NAND flash memory pool.

8. The storage device of claim 1 , wherein the interface comprises at least two independent links and wherein each link connects to its own NAND flash memory domain and link-selection by individual threads is done on the level of the host.

9. A method of operating the storage device of claim 1 , the method comprising monitoring the program and erase count of all blocks, partitioning the NAND flash memory space into a user memory pool and an over-provisioning pool, and assigning one or more blocks with the lowest program and erase count after an erase cycle to the over-provisioning pool.

10. The method of claim 9 , wherein blocks assigned to the over-provisioning pool are written to in single level cell mode, the majority of blocks in the user memory pool are configured in multilevel cell mode, and space reclamation uses multi-level cell mode blocks for coalescence of valid data.

11. The method of claim 9 , wherein blocks assigned to the over-provisioning pool are formatted to one of a plurality of mapping unit sizes.

12. The method of claim 9 , wherein some files are stored in a mapping unit and treated as a single object by the file system, and other files are stored in a plurality of mapping units and treated as composite objects.

13. The method of claim 9 , wherein files changed by the host are stored as partial updates changed parts of the files are stored in a new physical location, and metadata are updated to point to the new physical location of the partial update.

14. The method of claim 9 wherein, after an original file is updated, the original file is not invalidated but assigned a version control level.

Assignments (15)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2017
From: TOSHIBA CORPORATION
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043620/0430 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2016
From: OCZ STORAGE SOLUTIONS, INC.
To: TOSHIBA CORPORATION
Reel/Frame 038434/0371 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 030092/0739) Recorded Apr 8, 2014
From: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 032640/0284 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 031611/0168) Recorded Apr 8, 2014
From: COLLATERAL AGENTS, LLC
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 032640/0455 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE AND ATTACH A CORRECTED ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 032365 FRAME 0920. ASSIGNOR(S) HEREBY CONFIRMS THE THE CORRECT EXECUTION DATE IS JANUARY 21, 2014. Recorded Mar 18, 2014
From: OCZ TECHNOLOGY GROUP, INC.
To: TAEC ACQUISITION CORP.
Reel/Frame 032461/0486 →
CHANGE OF NAME Recorded Feb 27, 2014
From: TAEC ACQUISITION CORP.
To: OCZ STORAGE SOLUTIONS, INC.
Reel/Frame 032365/0945 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2014
From: OCZ TECHNOLOGY GROUP, INC.
To: TAEC ACQUISITION CORP.
Reel/Frame 032365/0920 →
SECURITY AGREEMENT Recorded Nov 11, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: COLLATERAL AGENTS, LLC
Reel/Frame 031611/0168 →
SECURITY AGREEMENT Recorded Mar 27, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
Reel/Frame 030092/0739 →
RELEASE OF SECURITY INTEREST Recorded Mar 26, 2013
From: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 030088/0443 →
SECURITY AGREEMENT Recorded May 14, 2012
From: OCZ TECHNOLOGY GROUP, INC.
To: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
Reel/Frame 028440/0866 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2011
From: SCHUETTE, FRANZ MICHAEL; CLAWSON, WILLIAM WARD
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 027184/0199 →