Reducing metastability in analog to digital conversion

1. A system for performing analog-to-digital conversion, comprising:

a sampling unit configured to generate multiple digital samples from an analog input signal at each recurrence of a periodic interval, the sampling unit comprising multiple analog-to-digital converters (ADCs) that operate in parallel to separately receive and digitize the analog input signal to produce the digital samples; and

a processing unit configured to combine the digital samples to produce a digital output signal, the processing unit configured to determine when any of the digital samples is an outlier by performing a pairwise comparison of the digital samples, identifying a digital sample as an outlier if it differs from each of the other digital samples by more than a predetermined amount and averaging digital samples that are not determined to be outliers.

2. The system of claim 1 , wherein the sampling unit further includes a sample and hold (S/H) circuit configured to sample the analog input signal and provide the sampled analog input signal to each of the multiple ADCs.

3. The system of claim 1 , wherein the sampling unit further includes multiple sample and hold (S/H) circuits each configured to sample the analog input signal and to provide the sampled analog input signal to a corresponding one of the multiple ADCs.

4. The system of claim 1 , further comprising multiple offset circuits each introducing an offset into the analog input signal provided to a corresponding one of the multiple ADCs.

5. The system of claim 1 , further comprising multiple offset circuits each configured to introduce an offset into an internal comparator of a corresponding one of the multiple ADCs.

6. The system of claim 1 , wherein the processing unit is further configured to produce an error signal indicating a reliability of the digital output signal.

7. The system of claim 6 , wherein the error signal indicates a number of outliers among the digital samples.

8. The system of claim 1 , wherein the multiple ADCs comprise three ADCs.

9. A method of performing analog to digital conversion, the method comprising:

sampling and digitizing an analog input signal to generate multiple digital samples at each recurrence of a periodic interval; and

combining the digital samples to generate a digital output signal, wherein combining the digital samples comprises determining whether any of the digital samples is an outlier by performing a pairwise comparison of the digital samples, identifying a digital sample as an outlier if it differs from each of the other digital samples by more than a predetermined amount, and ignoring any outliers when generating the digital output signal.

10. The method of claim 9 , wherein the digital output signal is generated as an average of the digital samples that are not outliers.

11. The method of claim 9 , wherein sampling and digitizing the analog input signal comprises:

transmitting the analog input signal to a plurality of analog to digital converters (ADCs) arranged in parallel.

12. The method of claim 11 , wherein sampling and digitizing the analog input signal further comprises:

transmitting the analog input signal to at least one sample and hold (S/H) circuit and then to the plurality of ADCs.

13. The method of claim 11 , further comprising applying a separate voltage offset to the analog input signal as transmitted to each of the ADCs, or to internal comparators of the ADCs.

14. The method of claim 11 , further comprising adjusting each of the digital samples according to a calibrated gain or offset of a corresponding one of the ADCs.

15. The method of claim 11 , further comprising adjusting each of the digital samples according to a calibrated timing error of a corresponding one of the ADCs.

16. The method of claim 9 , further comprising generating an error signal indicating whether any outliers were identified among the digital samples.