METHOD TO MATCH INPUT AND OUTPUT TIMESTAMPS IN A VIDEO ENCODER AND ADVERTISEMENT INSERTER
A method, a video processing system, and an electronic device are disclosed. A video transcoder may decode a compressed video data frame creating a decoded video data frame. The video transcoder may embed a network presentation timestamp in the decoded video data frame. The video transcoder may re-encode the decoded video data frame creating a transcoded video data frame. A field programmable gate array may compare the network presentation timestamp with a transcoder presentation timestamp to determine a timestamp offset.
1 . A machine-implemented method, comprising:
decoding a compressed video data frame in a video transcoder creating a decoded video data frame;
embedding a network presentation timestamp in the decoded video data frame;
re-encoding the decoded video data frame in the video transcoder creating a transcoded video data frame; and
comparing the network presentation timestamp with a transcoder presentation timestamp to determine a timestamp offset.
2 . The method of claim 1 , further comprising:
embedding the network presentation timestamp in a vertical blanking interval.
3 . The method of claim 1 , further comprising:
embedding the network presentation timestamp in a video frame header.
4 . The method of claim 1 , further comprising:
bypassing an associated audio data set around the video transcoder.
5 . The method of claim 4 , further comprising:
delaying the associated audio data set to match the transcoded video data frame.
6 . The method of claim 1 , further comprising:
tracking an input program clock reference with an input counter; and
tracking an output program clock reference with an output counter.
7 . The method of claim 6 , further comprising:
delaying an associated audio data set based on the input program clock reference and the output program clock reference.
8 . The method of claim 1 , further comprising:
inserting a local video stream using a splice timestamp.
9 . The method of claim 1 , further comprising:
identifying a switch frame using a splice timestamp.
10 . The method of claim 1 , further comprising:
switching to a compressed audio data set using a splice timestamp.
11 . The method of claim 1 , further comprising:
switching to a pulse code modulated audio data set using a splice timestamp.
12 . A video processing system comprising:
a network video channel input that receives a compressed video data frame with a network presentation timestamp;
a video transcoder that decodes the compressed video data frame creating a decoded video data frame, embeds the network presentation timestamp in the decoded video data frame, and re-encodes the decoded video data frame creating a transcoded video data frame.
13 . The video processing system of claim 12 , wherein the video transcoder embeds the network presentation timestamp in a vertical blanking interval.
14 . The video processing system of claim 12 , wherein the video transcoder embeds the network presentation timestamp in a header stuffing.
15 . The video processing system of claim 12 , further comprising:
an audio data bypass that receives an associated audio data set around the video transcoder.
16 . The video processing system of claim 15 , wherein the audio data bypass delays the associated audio data set to match the compressed video data frame.
17 . The video processing system of claim 12 , further comprises:
a field programmable gate array that compares the network presentation timestamp with a transcoder presentation timestamp to determine a timestamp offset.
18 . The video processing system of claim 12 , further comprising:
a local video channel input that receives a local video stream for insertion after the compression video data frame.
19 . A electronic device, comprising:
a network video channel input that receives a compressed video data frame;
a video transcoder that decodes the compressed video data frame and re-encodes the compressed video data frame.
an input counter that tracks an input program clock reference; and
an output counter that tracks an output program clock reference.
20 . The electronic device of claim 19 , further comprising:
an audio data bypass that delays an associated audio data set based on the input program clock reference and the output program clock reference.