IP Library Granted Patent US 8,787,582
Granted Patent B2
US 8,787,582 · App. 13/253,591 · Granted Jul 22, 2014

Key implementation system

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Quick Facts
Patent No.
US 8,787,582
App. No.
13/253,591
Granted
Jul 22, 2014
Kind
B2
Abstract

An LSI includes a first decryptor which receives first encrypted key data, and decrypts the first encrypted key data using a first cryptographic key, thereby generating first decrypted key data, a second cryptographic key generator which generates a second cryptographic key based on a second ID, a second encryptor which encrypts the first decrypted key data using the second cryptographic key, thereby generating second encrypted key data, and a second decryptor which decrypts the second encrypted key data using the second cryptographic key, thereby generating second decrypted key data. At a time of key setting, the second encryptor stores the second encrypted key data in a storage unit. At a time of key usage, the second decryptor reads the second encrypted key data from the storage unit.

Claims (81)

1. A key implementation system, comprising:

a large-scale integrated circuit (LSI); and

a storage unit, wherein:

the LSI includes:

a first decryptor configured to receive first encrypted key data, and to decrypt the first encrypted key data using a first cryptographic key, thereby generating first decrypted key data;

a second cryptographic key generator configured to generate a second cryptographic key based on a second ID;

a second encryptor configured to encrypt the first decrypted key data using the second cryptographic key, thereby generating second encrypted key data, and to store the second encrypted key data in the storage unit; and

a second decryptor configured to read the second encrypted key data that has been stored by the second encryptor from the storage unit, and decrypt the second encrypted key data using the second cryptographic key, thereby generating second decrypted key data, and

at a time of key setting, the second encryptor stores the second encrypted key data in the storage unit, and at a time of key usage, the second decryptor reads the second encrypted key data from the storage unit.

2. The key implementation system of claim 1 , wherein

the LSI includes a first cryptographic key generator configured to generate the first cryptographic key based on a first ID.

3. The key implementation system of claim 2 , wherein

the first cryptographic key generator generates the first cryptographic key based on a first LSI key and the first ID, and

the second cryptographic key generator generates the second cryptographic key based on a second LSI key and the second ID.

4. The key implementation system of claim 2 , wherein

the first ID has a different value for every predetermined number of the LSIs, and

the second ID has a different value for each LSI.

5. The key implementation system of claim 2 , wherein

the LSI holds ID data including first partial data, second partial data, and third partial data,

the first ID includes the first and the third partial data, and

the second ID includes the second and the third partial data.

6. The key implementation system of claim 2 , wherein

the first ID is held in the storage unit, and

the second ID is held in the LSI.

7. The key implementation system of claim 1 , wherein

the first decrypted key data includes verification data, and

the LSI includes a first verifier configured to confirm the verification data, and to verify a validity of the first decrypted key data.

8. The key implementation system of claim 1 , wherein

the second decrypted key data includes verification data, and

the LSI includes a second verifier configured to confirm the verification data, and to verify a validity of the second decrypted key data.

9. The key implementation system of claim 1 , comprising:

a content decryption processor configured to perform, using the second decrypted key data, authentication processing in relation to access to encrypted content, or decryption processing of encrypted content.

10. A large-scale integrated circuit (LSI), comprising:

a second cryptographic key generator configured to generate a second cryptographic key based on a second ID;

a first decryptor configured to receive first encrypted key data, and to decrypt the first encrypted key data using a first cryptographic key, thereby generating first decrypted key data;

a second encryptor configured to encrypt the first decrypted key data using the second cryptographic key, thereby generating second encrypted key data, and to store the second encrypted key data in an external storage unit; and

a second decryptor configured to read the second encrypted key data that has been stored by the second encryptor from the external storage unit, and decrypt the second encrypted key data using the second cryptographic key, thereby generating second decrypted key data,

wherein at a time of key setting, the second encryptor stores the second encrypted key data in the external storage unit, and at a time of key usage, the second decryptor reads the second encrypted key data from the external storage unit.

11. The LSI of claim 10 , further comprising:

a first cryptographic key generator configured to generate the first cryptographic key based on a first ID.

12. The LSI of claim 11 , wherein:

the first cryptographic key generator generates the first cryptographic key based on a first LSI key and the first ID, and

the second cryptographic key generator generates the second cryptographic key based on a second LSI key and the second ID.

13. The LSI of claim 11 , wherein:

the LSI holds ID data including first partial data, second partial data, and third partial data,

the first ID includes the first and the third partial data, and

the second ID includes the second and the third partial data.

14. The LSI of claim 11 , wherein

the first ID is held in the storage unit, and

the second ID is held in the LSI.

15. The LSI of claim 10 , wherein:

the first decrypted key data includes verification data, and

the LSI includes a first verifier configured to confirm the verification data, and to verify a validity of the first decrypted key data.

16. The LSI of claim 10 , wherein:

the second decrypted key data includes verification data, and

the LSI includes a second verifier configured to confirm the verification data, and to verify a validity of the second decrypted key data.

17. The LSI of claim 10 , further comprising:

a content decryption processor configured to perform, using the second decrypted key data, authentication processing in relation to access to encrypted content, or decryption processing of encrypted content.

18. A key implementation system, comprising:

a large-scale integrated circuit (LSI); and

a storage unit, wherein:

the LSI includes:

a first decryptor configured to receive first encrypted key data, and to decrypt the first encrypted key data using an LSI key, thereby generating first decrypted key data;

a second cryptographic key generator configured to generate a second cryptographic key based on an ID;

a second encryptor configured to encrypt the first decrypted key data using the second cryptographic key, thereby generating second encrypted key data, and to store the second encrypted key data in the storage unit; and

a second decryptor configured to read the second encrypted key data that has been stored by the second encryptor from the storage unit, and decrypt the second encrypted key data using the second cryptographic key, thereby generating second decrypted key data, and

at a time of key setting, the second encryptor stores the second encrypted key data in the storage unit, and at a time of key usage, the second decryptor reads the second encrypted key data from the storage unit.

19. The key implementation system of claim 18 , wherein

the LSI key and the ID is held in the LSI.

20. The key implementation system of claim 18 , further comprising:

a content decryption processor configured to perform, using the second decrypted key data, authentication processing in relation to access to encrypted content, or decryption processing of encrypted content.

21. A large-scale integrated circuit (LSI), comprising:

a second cryptographic key generator configured to generate a second cryptographic key based on an ID;

a first decryptor configured to receive first encrypted key data, and to decrypt the first encrypted key data using an LSI key, thereby generating first decrypted key data;

a second encryptor configured to encrypt the first decrypted key data using the second cryptographic key, thereby generating second encrypted key data, and to store the second encrypted key data in an external storage unit; and

a second decryptor configured to read the second encrypted key data that has been stored by the second encryptor from the external storage unit, and decrypt the second encrypted key data using the second cryptographic key, thereby generating second decrypted key data,

wherein at a time of key setting, the second encryptor stores the second encrypted key data in the external storage unit, and at a time of key usage, the second decryptor reads the second encrypted key data from the external storage unit.

22. The LSI of claim 21 , wherein

the LSI key and the ID is held in the LSI.

23. The LSI of claim 21 , further comprising:

a content decryption processor configured to perform, using the second decrypted key data, authentication processing in relation to access to encrypted content, or decryption processing of encrypted content.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0870 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2011
From: YOKOTA, KAORU; KATSURA, AKIHITO; NEMOTO, YUSUKE; TORISAKI, YUISHI; FUJIWARA, MAKOTO
To: PANASONIC CORPORATION
Reel/Frame 027158/0001 →