Document validator with power management

1. A low power validator for validating documents of value comprising:

a processing unit for controlling operation of the validator;

an inlet for receiving a document of value from a user; and

a power management system for transitioning the validator between a power conserving mode and a normal operating mode, wherein the power management system comprises a wake up unit arranged to monitor the inlet for the presence of a document of value and to monitor a voltage provided from a power source, the power management system adapted such that the validator can be transitioned from the power conserving mode to the normal operating mode without having to be reset after the voltage provided from the power source was measured to be below a predetermined threshold;

wherein the validator is arranged to transition from the normal operating mode to the power conserving mode when the monitored voltage provided from the power source falls below the predetermined threshold and based on receipt of an instruction signal by the wakeup unit;

wherein the validator is arranged to transition from the power conserving mode to the normal operating mode when the wake up unit detects the presence of a document of value in the inlet and the voltage provided from the power source is measured to be above the predetermined threshold.

2. The low power validator according to claim 1 further comprising a power detection unit operatively coupled to the wake up unit to provide a measurement of the power source upon receiving a driving signal from the wake up unit.

3. The low power validator according to claim 2 , wherein the power detection unit further comprises a voltage divider and adapted to measure the voltage provided from the power source using the voltage divider.

4. The low power validator according to claim 1 , wherein the wake up unit includes a micro-processor.

5. The low power validator according to claim 4 , wherein a voltage divider is designed and arranged to prevent excess voltage to be sensed by the micro-processor.

6. The low power validator according to claim 4 , wherein the micro-processor is arranged to, when the voltage provided from the power source is measured to be above the predetermined threshold and when the wake up unit detects the presence of a document of value in the inlet, provide an enable signal to a switch such that the validator is transitioned from the power conserving mode to the normal operating mode.

7. The low power validator according to claim 6 , wherein the switch comprises a P-FET, especially the switch comprises a P-FET and an N-FET wherein the enable signal is provided to a gate terminal of the N-FET, a source terminal of the N-FET is connected to ground, a drain terminal of the N-FET is connected to a gate terminal of the P-FET, a source terminal of the P-FET is connected to the power source and a drain terminal of the P-FET is connected to a sensing unit of the validator.

8. The low power validator according to claim 1 , wherein the validator further comprises a photo-emitter and a photo-detector arranged to detect the presence of a document of value in the inlet.

9. The low power validator according to claim 8 , wherein the photo-emitter and the photo-detector are arranged on opposite sides of a path of a document of value in the inlet or on the same side of the path.

10. The low power validator according to claim 1 wherein the power source is a 12-volt DC battery.

11. The low power validator according to claim 1 wherein the processing unit includes a microprocessor.

12. The low power validator according to claim 11 wherein the validator is arranged to transition from a normal operating mode to a power conserving mode upon receipt of an instruction signal from the validator microprocessor by the wake up unit.

13. The low power validator according to claim 11 , wherein the microprocessor continuously monitors the voltage provided from the power source during normal operating mode.

14. A method for controlling the operation of a low power validator for validating documents of value comprising:

controlling the operation of the validator using a processing unit for receiving a document of value from a user by an inlet; and

transitioning the validator between a power conserving mode and a normal operating mode using a power management system, wherein the inlet is monitored for the presence of a document of value, a voltage provided from a power source is monitored using a wake up unit comprised in the power management system, the validator transitions from the power conserving mode to the normal operating mode when the wake up unit detects the presence of a document of value in the inlet and the voltage provided from the power source is measured to be above a predetermined threshold, and the validator can be transitioned from the power conserving mode to the normal operating mode without having to be reset after the voltage provided from the power source was measured to be below the predetermined threshold;

wherein the validator is transitioned from the normal operating mode to the power conserving mode when the monitored voltage provided from the power source falls below the predetermined threshold and based on receipt of an instruction signal by the wakeup unit.

15. The method according to claim 14 , wherein the power source is measured, upon receiving a driving signal from the wake up unit, by a power detection unit operatively coupled to the wake up unit.

16. The method according to any or the claims 15 , wherein the power detection unit further comprises a voltage divider and the power detection unit is adapted to measure the voltage provided from the power source using the voltage divider.

17. The method according to claim 16 , wherein excess voltage to be sensed by a micro-processor included in the wake up unit is prevented by the voltage divider.

18. The method according to claim 17 , wherein, when the voltage provided from the power source is measured to be above the predetermined threshold and when the wake up unit detects the presence of a document of value in the inlet, the micro-processor is arranged provides an enable signal to a switch such that the validator is transitioned from the power conserving mode to the normal operating mode.

19. The method according to claim 18 , wherein the switch comprises a P-FET, especially the switch comprises a P-FET and an N-FET wherein the enable signal is provided to a gate terminal of the N-FET, a source terminal of the N-FET is connected to ground, a drain terminal of the N-FET is connected to a gate terminal of the P-FET, a source terminal of the P-FET is connected to the power source and a drain terminal of the P-FET is connected to a sensing unit of the validator.

20. The method according to claim 14 , wherein the presence of a document of value in the inlet is detected using a photo-emitter and a photo-detector.

21. The method according to claim 14 , wherein voltage provided by the power source is provided by a 12-volt DC battery.

22. The method according to claim 14 , using a microprocessor in the processing unit.

23. The method according to claim 22 , wherein the validator is transitioned from a normal operating mode to a power conserving mode upon receipt of an instruction signal from the validator microprocessor by the wake up unit.

24. The method according to claim 22 , wherein the microprocessor continuously monitors the voltage provided from the power source during normal operating mode.

25. A low power validator for validating documents of value comprising:

a processing unit for controlling operation of the validator;

an inlet for receiving a document of value from a user; and

a power management system for transitioning the validator between a power conserving mode and a normal operating mode, wherein the power management system comprises a wake up unit arranged to monitor the inlet for the presence of a document of value and to monitor a voltage provided from a power source;

wherein the validator is arranged to transition from the normal operating mode to the power conserving mode based on receipt of an instruction signal from a validator microprocessor by the wake up unit and when the monitored voltage provided from the power source falls below a predetermined threshold;

wherein the validator is arranged to transition from the power conserving mode to the normal operating mode when the wake up unit detects the presence of a document of value in the inlet and the voltage provided from the power source is measured to be above the predetermined threshold and the power management system is adapted such that the validator can be transitioned from the power conserving mode to the normal operating mode without having to be reset after the voltage provided from the power source was measured to be below the predetermined threshold.

26. The low power validator according to claim 25 further comprising a power detection unit operatively coupled to the wake up unit to provide a measurement of the power source upon receiving a driving signal from the wake up unit.

27. The low power validator according to claim 26 , wherein the power detection unit further comprises a voltage divider and adapted to measure the voltage provided from the power source using the voltage divider.

28. The low power validator according to claim 25 , wherein the wake up unit includes a micro-processor.

29. The low power validator according to claim 28 , wherein a voltage divider is designed and arranged to prevent excess voltage to be sensed by the micro-processor.

30. The low power validator according to claim 28 , wherein the micro-processor is arranged to, when the voltage provided from the power source is measured to be above the predetermined threshold and when the wake up unit detects the presence of a document of value in the inlet, provide an enable signal to a switch such that the validator is transitioned from the power conserving mode to the normal operating mode.

31. The low power validator according to claim 30 , wherein the switch comprises a P-FET, especially the switch comprises a P-FET and an N-FET wherein the enable signal is provided to a gate terminal of the N-FET, a source terminal of the N-FET is connected to ground, a drain terminal of the N-FET is connected to a gate terminal of the P-FET, a source terminal of the P-FET is connected to the power source and a drain terminal of the P-FET is connected to a sensing unit of the validator.

32. The low power validator according to claim 25 , wherein the validator further comprises a photo-emitter and a photo-detector arranged to detect the presence of a document of value in the inlet.

33. The low power validator according to claim 32 , wherein the photo-emitter and the photo-detector are arranged on opposite sides of a path of a document of value in the inlet or on the same side of the path.

34. The low power validator according to claim 25 wherein the power source is a 12-volt DC battery.

35. The low power validator according to claim 25 wherein the processing unit includes a microprocessor.

36. A method for controlling the operation of a low power validator for validating documents of value comprising:

controlling the operation of the validator using a processing unit for receiving a document of value from a user by an inlet;

transitioning the validator from a normal operating mode and a power conserving mode using a power management system upon receipt of an instruction signal from a validator microprocessor by a wake up unit and when a voltage provided from a power source falls below a predetermined threshold, wherein the inlet is monitored for the presence of a document of value, and wherein the voltage provided from the power source is monitored using the wake up unit comprised in the power management system,

wherein the validator transitions from the power conserving mode to the normal operating mode when the wake up unit detects the presence of a document of value in the inlet and the voltage provided from the power source is measured to be above the predetermined threshold and the validator can be transitioned from the power conserving mode to the normal operating mode without having to be reset after the voltage provided from the power source was measured to be below the predetermined threshold.

37. The method according to claim 36 , wherein the power source is measured, upon receiving a driving signal from the wake up unit, by a power detection unit operatively coupled to the wake up unit.

38. The method according to any or the claims 37 , wherein the power detection unit further comprises a voltage divider and the power detection unit is adapted to measure the voltage provided from the power source using the voltage divider.

39. The method according to claim 38 , wherein excess voltage to be sensed by a micro-processor included in the wake up unit is prevented by the voltage divider.

40. The method according to claim 39 , wherein, when the voltage provided from the power source is measured to be above the predetermined threshold and when the wake up unit detects the presence of a document of value in the inlet, the micro-processor is arranged to provide an enable signal to a switch such that the validator is transitioned from the power conserving mode to the normal operating mode.

41. The method according to claim 40 , wherein the switch comprises a P-FET, especially the switch comprises a P-FET and an N-FET wherein the enable signal is provided to a gate terminal of the N-FET, a source terminal of the N-FET is connected to ground, a drain terminal of the N-FET is connected to a gate terminal of the P-FET, a source terminal of the P-FET is connected to the power source and a drain terminal of the P-FET is connected to a sensing unit of the validator.

42. The method according to claim 36 , wherein the presence of a document of value in the inlet is detected using a photo-emitter and a photo-detector.

43. The method according to claim 36 , wherein voltage provided by the power source is provided by a 12-volt DC battery.

44. The method according to claim 36 , using a microprocessor in the processing unit.

45. The method according to claim 44 , wherein the microprocessor continuously monitors the voltage provided from the power source during normal operating mode.