Method and device for decoding Reed-Solomon (RS) code

1. A method for decoding an RS (Reed-Solomon) code, the method comprising:

receiving bit reliability information of the RS code output by a channel; and performing a hard decision on the received bit reliability information to obtain a hard-decision result value sequence;

determining a type of an error of the hard-decision result value sequence according to an initial check array corresponding to an encoding mode of the RS code;

according to preset corresponding relationships between types of errors of the hard-decision result value sequence and error-correcting modes capable of correcting the errors, determining an error-correcting mode corresponding to the type of the error of the hard-decision result value sequence, and performing a bit error correction on the hard-decision result value sequence according to the determined error-correcting mode;

outputting the hard-decision result value sequence after the bit error correction as a decoding result.

2. The method according to claim 1 , wherein, the step of determining a type of an error of the hard-decision result value sequence according to an initial check array corresponding to an encoding mode of the RS code is:

sequencing reliability numerical values comprised in the bit reliability information;

selecting (n-k) columns corresponding to (n-k) smallest reliability numerical values after the sequencing from the initial check array, and converting the selected (n-k) columns to a unit array to obtain a new check array, wherein, the n is a binary code length of the RS code, and the k is a binary information length of the RS code before being encoded;

determining that the type of the error of the hard-decision result value sequence is a low reliability error or a mixed type error according to the new check array.

3. The method according to claim 2 , wherein, the step of determining that the type of the error of the hard-decision result value sequence is a low reliability error or a mixed type error according to the new check array is:

A, constituting a hard-decision vector having a same number of rows as the new check array by every hard-decision result value in the hard-decision result value sequence;

B, calculating a product of the new check array and the current hard-decision vector, and performing a modulo 2 operation on the product result to obtain an adjoint vector; determining a number of 1 in the adjoint vector, and taking the determined number as an adjoint vector weight;

C, judging whether the adjoint vector weight is less than a preset threshold value, and if yes, determining that the type of the error of the hard-decision result value sequence is the low reliability error; or else, determining that the type of the error of the hard-decision result value sequence is the mixed type error.

4. The method according to claim 3 , wherein, when the type of the error of the hard-decision result value sequence is the low reliability error, the error-correcting mode corresponding to the low reliability error is:

searching the adjoint vector for rows whose numerical values are 1, and determining columns whose numeral values are 1 in the found rows in the new check array;

flipping bits corresponding to the columns in the hard-decision result value sequence.

5. The method according to claim 3 , wherein, when the type of the error of the hard-decision result value sequence is the low reliability error, the error-correcting mode corresponding to the low reliability error is:

recoding and calculating check bits by taking high reliability bits in the hard-decision result value sequence as information bits and the new check array as a check warranty, and updating low reliability bits in the hard-decision result value sequence using obtained the check bits;

wherein, the low reliability bits are the bits corresponding to the (n-k) information having the smallest numerical values after sequencing the bit reliability information, and the high reliability bits are k bits other than the bits corresponding to the (n-k) information having the smallest numerical values.

6. The method according to claim 3 , wherein, when the type of the error of the hard-decision result value sequence is the mixed type error, the error-correcting mode corresponding to the mixed type error is:

for each of columns other than the (n-k) columns in the new check array, calculating an associated value of each column with the current adjoint vector;

selecting a maximum associated value obtained by calculation, determining columns in the new check array used for calculating the maximum associated value, and flipping bits in the current hard-decision vector corresponding to the determined columns, and returning to step B.

7. The method according to claim 3 , wherein, the preset threshold value is a threshold value corresponding to the initial check array of the RS code obtained by simulation.

8. A device for decoding an RS (Reed-Solomon) code, comprising a channel information receiving unit, a hard-decision unit, an error type determining unit, a bit error correcting unit and a decoding result outputting unit; wherein,

the channel information receiving unit is configured to receive bit reliability information of the RS code output by a channel;

the hard-decision unit is configured to perform a hard decision on the bit reliability information to obtain a hard-decision result value sequence;

the error type determining unit is configured to determine a type of an error of the hard-decision result value sequence according to an initial check array corresponding to an encoding mode of the RS code;

the bit error correcting unit is configured to, according to preset corresponding relationships between types of errors of the hard-decision result value sequence and error-correcting modes capable of correcting the errors, determine an error-correcting mode corresponding to the type of the error of the hard-decision result value sequence, and perform a bit error correction on the hard-decision result value sequence according to the determined error-correcting mode;

the decoding result outputting unit is configured to output the hard-decision result value sequence after the bit error correcting unit performing the bit error correction as a decoding result.

9. The device according to claim 8 , wherein, the error type determining unit comprises a reliability sequencing unit, a check array Gaussian eliminating unit and an error type classifying unit; wherein,

the reliability sequencing unit is configured to sequence reliability numerical values comprised in the bit reliability information;

the check array Gaussian eliminating unit is configured to select (n-k) columns corresponding to (n-k) smallest reliability numerical values after the sequencing from the initial check array, and convert the selected (n-k) columns to a unit array to obtain a new check array, wherein, the n is a binary code length of the RS code, and the k is a binary information length of the RS code before being encoded;

the error type classifying unit is configured to determine that the type of the error of the hard-decision result value sequence is a low reliability error or a mixed type error according to the new check array.

10. The device according to claim 9 , wherein, the error type classifying unit comprises an adjoint weight calculating unit and a threshold deciding unit; wherein,

the adjoint weight calculating unit is configured to constitute a hard-decision vector having a same number of rows as the new check array by each hard-decision result value in the hard-decision result value sequence, calculate a product of the new check array and the current hard-decision vector, and perform a modulo 2 operation on the product result to obtain an adjoint vector; determine a number of 1 in the adjoint vector, and take the determined number as an adjoint vector weight;

the threshold deciding unit is configured to judge whether the adjoint vector weight is less than a preset threshold value, and if yes, determine that the type of the error of the hard-decision result value sequence is the low reliability error; or else, determine that the type of the error of the hard-decision result value sequence is the mixed type error.

11. The device according to claim 10 , wherein, the bit error correcting unit comprises a first low reliability error decoding unit and/or a second low reliability error decoding unit, wherein:

the first low reliability error decoding unit is configured to search the adjoint vector for rows whose numerical values are 1, and determine columns whose numeral values are 1 in the found rows in the new check array; flip bits corresponding to the columns in the hard-decision result value sequence;

the second low reliability error decoding unit is configured to recode and calculate check bits by taking high reliability bits in the hard-decision result value sequence as information bits and the new check array as a check warranty, and update low reliability bits in the hard-decision result value sequence using obtained the check bits; wherein, the low reliability bits are the bits corresponding to the (n-k) information having the smallest numerical values after sequencing the bit reliability information, and the high reliability bits are k bits other than the bits corresponding to the (n-k) information having the smallest numerical values.

12. The device according to claim 10 , wherein, the bit error-correcting unit comprises a first mixed type error decoding unit and/or a second mixed type error decoding unit, wherein:

the first mixed type error decoding unit is configured to, for each of columns other than the (n-k) columns in the new check array, calculate an associated value of each column to the current adjoint vector; select a maximum associated value obtained by calculation, determine columns in the new check array used for calculating the maximum associated value, and flip bits in the current hard-decision vector corresponding to the determined columns, and trigger the adjoint weight calculating unit;

the second mixed type error decoding unit is configured to output the hard-decision result value sequence as a decoding result.

13. The device according to claim 10 , wherein, the preset threshold value is a threshold value corresponding to the initial check array of the RS code obtained by simulation.

14. The method according to claim 4 , wherein, the preset threshold value is a threshold value corresponding to the initial check array of the RS code obtained by simulation.

15. The method according to claim 5 , wherein, the preset threshold value is a threshold value corresponding to the initial check array of the RS code obtained by simulation.

16. The method according to claim 6 , wherein, the preset threshold value is a threshold value corresponding to the initial check array of the RS code obtained by simulation.

17. The device according to claim 11 , wherein, the preset threshold value is a threshold value corresponding to the initial check array of the RS code obtained by simulation.

18. The device according to claim 12 , wherein, the preset threshold value is a threshold value corresponding to the initial check array of the RS code obtained by simulation.