Subprocessor, integrated circuit device, and electronic apparatus
A subprocessor, an integrated circuit device, and an electronic apparatus or the like capable of performing data processing efficiently are provided. A subprocessor is connected to a host processor through a bus controller. The subprocessor includes: a command fetch unit that fetches a command from a subprocessor program; a register unit; a command decoding unit that decodes the command; and an operation unit that performs command execution processing. The host processor sets a program counter value indicating a storage destination of the subprocessor program and a processing start command for, the processing of the subprocessor to the register unit. The command fetch unit fetches a command designated by the program counter value, the command decoding unit decodes the command, and the operation unit performs command execution processing.
1. An integrated circuit device comprising:
a bus controller;
a clock generation circuit configured to supply and stop supplying clock to a host processor; and
a subprocessor connected to the host processor through the bus controller,
the subprocessor including:
a command fetch unit that fetches a command from a subprocessor program;
a register unit;
a command decoding unit that decodes the command from the subprocessor program; and
an operation unit that performs command execution processing based on an output of the command decoding unit,
the host processor setting a program counter value indicating a storage destination of the subprocessor program and a processing start command for a processing of the subprocessor to the register unit,
the command fetch unit fetching a first command designated by the program counter value,
the command decoding unit decoding the first command,
the operation unit performing the command execution processing,
the bus controller being connected to the subprocessor and the host processor,
the bus controller performing bus control between a memory in which a host processor program and the subprocessor program are stored, the host processor, and the subprocessor,
when a processing end command of the subprocessor program is decoded, the subprocessor issuing a processing complete signal,
upon the host processor issuing the processing start command and the processing of the subprocessor being executed by the subprocessor, the host processor issuing a stop signal to the clock generation circuit to stop the clock generation circuit from supplying clock to the host processor, and
the clock generation circuit, after stopping supplying clock, resuming the supply of clock to the host processor upon receiving the processing complete signal issued from the subprocessor.
2. The integrated circuit device according to claim 1 , further comprising a bus controller interface that performs interface processing between the bus controller and the subprocessor.
3. The integrated circuit device according to claim 2 ,
the bus controller interface including a host interface that performs interface processing between the host processor and the subprocessor.
4. The integrated circuit device according to claim 2 ,
the bus controller interface including a data interface for reading or writing data for execution of a command.
5. The integrated circuit device according to claim 2 ,
the register unit including a data register, and
the operation unit performing command execution processing based on data which is written to the data register through the bus controller interface and the output of the command decoding unit.
6. The integrated circuit device according to claim 2 ,
the register unit including an address register that stores address information of data which is read or written through the bus controller interface, and
the address information of the address register being written by the host processor through the bus controller interface.
7. The integrated circuit device according to claim 1 ,
the register unit includes a control register that includes a Run bit indicating that the subprocessor being under processing, and
the Run bit being cleared when the processing complete signal is output.
8. The integrated circuit device according to claim 1 ,
the register unit including an operation parameter register,
when an operation parameter being written to the operation parameter register by the host processor, the operation unit performs operation processing in accordance with the content set by the operation parameter.
9. The integrated circuit device according to claim 1 ,
the register unit including an operation parameter register, and
when an operation parameter is written to the operation parameter register in accordance with an operation parameter setting command of the subprocessor program, the operation unit performing operation processing in accordance with the content set by the operation parameter.
10. The integrated circuit device according to claim 1 , further comprising the host processor.
11. An electronic apparatus comprising the integrated circuit device according to claim 1 .
12. The integrated circuit device according to claim 3 ,
the bus controller interface including a data interface for reading or writing data for execution of a command.
13. The integrated circuit device according to claim 3 ,
the register unit including a data register, and
the operation unit performing command execution processing based on data which is written to the data register through the bus controller interface and the output of the command decoding unit.
14. An electronic apparatus comprising the integrated circuit device according to claim 10 .
15. An electronic apparatus comprising the integrated circuit device according to claim 8 .
16. An electronic apparatus comprising the integrated circuit device according to claim 9 .