IP Library Granted Patent US 9,229,859
Granted Patent B2
US 9,229,859 · App. 13/259,127 · Granted Jan 5, 2016

Mapping non-prefetchable storage locations into memory mapped input/output space

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,229,859
App. No.
13/259,127
Granted
Jan 5, 2016
Kind
B2
Abstract

A system including a host and a device. The device has at least one non-prefetchable storage location. The host and the device are configured to map the at least one non-prefetchable storage location into memory mapped input/output space that is addressed via greater than 32 address bits.

Claims (31)

1. A system comprising:

a serial communication link;

a host coupled to the serial communication link; and

a device coupled to the serial communication link having at least one non-prefetchable storage location, wherein the host and the device are configured to map the at least one non-prefetchable storage location into memory mapped input/output space that is addressed via greater than 32 address bits based on system policy that ensures one of:

1) no bridges are in the system; and

2) a) the device is coupled to the host without an intervening bridge, and b) devices below a bridge are prohibited from doing peer-to-peer requests.

2. The system of claim 1 , wherein the host and the device are configured to determine whether the device is coupled to the host via an intervening bridge.

3. The system of claim 1 , wherein the serial communication link comprises a peripheral component interconnect express link.

4. The system of claim 3 , wherein a bridge is coupled to the peripheral component interconnect express link and the host and the device are configured to determine whether the device is below the bridge prior to mapping the at least one non-prefetchable storage location into the memory mapped input/output space.

5. The system of claim 3 , wherein the host and the device are configured to map the at least one non-prefetchable storage location into peripheral component interconnect express memory mapped input/output space via a base address register.

6. The system of claim 5 , wherein the base address register is a 64-bit base address register.

7. The system of claim 1 , wherein system policy states that devices below a bridge are prohibited from doing peer-to-peer requests.

8. A system comprising:

a peripheral component interconnect express link;

a device coupled to the peripheral component interconnect express link and including a base address register that maps non-prefetchable storage locations in the device to peripheral component interconnect express memory space; and

a host coupled to the peripheral component interconnect express link, wherein the device and the host are configured to map at least one of the non-prefetchable storage locations to greater than four giga-bytes of memory mapped input/output space in the peripheral component interconnect express memory space based on system policy that ensures one of:

1) no bridges are in the system; and

2) a) the device is coupled to the host without an intervening bridge, and b) devices below a bridge are prohibited from doing peer-to-peer requests.

9. The system of claim 8 , wherein the device and the host are configured to determine that the device is coupled to the host without an intervening bridge.

10. The system of claim 8 , wherein system policy states that devices are prohibited from being coupled to the peripheral component interconnect express link via a bridge.

11. The system of claim 8 , wherein system policy states that devices below a bridge are prohibited from doing peer-to-peer requests.

12. A method comprising:

mapping at least one non-prefetchable storage location of a device into peripheral component interconnect express memory space that is greater than four giga-bytes of memory mapped input/output space based on system policy that ensures one of:

1) no bridges are in the system; and

2) a) the device is coupled to the host without an intervening bridge, and b) devices below a bridge are prohibited from doing peer-to-peer requests.

13. The method of claim 12 , comprising:

determining whether a host is coupled to the device via an intervening bridge.

14. The method of claim 12 , comprising:

determining whether the device is coupled to a peripheral component interconnect express link via a bridge coupled to the peripheral component interconnect express link, prior to mapping the at least one non-prefetchable storage location into the peripheral component interconnect express memory space.

15. The method of claim 12 , comprising:

prohibiting devices below a bridge from doing peer-to-peer requests.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2021
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP; HEWLETT PACKARD ENTERPRISE COMPANY
To: VALTRUS INNOVATIONS LIMITED
Reel/Frame 055360/0424 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2011
From: COWAN, JOE P; CASIM, KAMRAN H
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 027079/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2011
From: COWAN, JOE P.
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 026954/0371 →