P-type semiconductor devices
View Patent ↗A semiconductor device comprises an active layer above a first confinement layer. The active layer comprises a layer of α-Sn less than 20 nm thick. The first confinement layer is formed of material with a wider band gap than α-Sn, wherein the band gap offset between α-Sn and this material allows confinement of charge carriers in the active layer so that the active layer acts as a quantum well. A similar second confinement layer may be formed over the active layer. This semiconductor device may be a p-FET. A method of fabricating such a semiconductor device is described.
1. A semiconductor device comprising:
an active layer comprising a layer of α-Sn less than 20 nm thick;
a first confinement layer below the active layer, wherein the first confinement layer is formed of a material or materials with a wider band gap than α-Sn, wherein the band gap offset between α-Sn and said material or materials allows confinement of charge carriers in the active layer so that the active layer acts as a quantum well;
a second confinement layer above the active layer;
a source;
a drain; and
a gate, the source, the drain and the gate all disposed over the second confinement layer, such that the gate is positioned between the source and the drain to control current in a p-channel between the source and the drain;
wherein the semiconductor device is a p-FET.
2. A semiconductor device as claimed in claim 1 , wherein the second confinement layer is also formed of a material or materials with a wider band gap than α-Sn, wherein the band gap offset between α-Sn and said material or materials allows confinement of charge carriers in the active layer.
3. A semiconductor device as claimed in claim 1 , wherein the active layer is doped with up to 2% of Si, Ge or a combination thereof.
4. A semiconductor device as claimed in claim 1 , wherein the charge carriers in the active layer are holes, and the active layer forms a p-channel.
5. A semiconductor device as claimed in claim 2 , wherein there is at least 1% of strain between the active layer and at least one of the first confinement layer and the second confinement layer.
6. A semiconductor device as claimed in claim 2 , wherein at least one of the first confinement layer and the second confinement layer comprises a ternary III-V semiconductor.
7. A semiconductor device as claimed in claim 6 , wherein at least one of the first confinement layer and the second confinement layer comprises Al x In 1-x Sb, wherein the value of x lies in the range 0≦x≦1.
8. A semiconductor device as claimed in claim 7 , wherein both the first confinement layer and the second confinement layer comprise Al x In 1-x Sb, wherein the value of x lies in the range 0≦x≦1.
9. A semiconductor device as claimed in claim 7 , wherein the value of x lies in the range 0.30≦x≦0.45.
10. A semiconductor device as claimed in claim 1 further comprising a substrate, wherein the first confinement layer forms a buffer layer of at least 0.2 μm over the substrate.
11. A semiconductor device as claimed in claim 10 , wherein the substrate comprises GaAs or Si.
12. A semiconductor device as claimed in claim 1 , wherein the semiconductor device further comprises a dopant sheet adapted to contribute charge carriers to the active layer.
13. A method of fabricating a semiconductor device, wherein the semiconductor device is a p-FET, comprising the steps of:
preparing a substrate;
growing a first confinement layer directly or indirectly on the substrate by an epitaxial growth process;
growing an active layer of α-Sn over the first confinement layer by an epitaxial growth process;
growing a second confinement layer over the active layer of α-Sn by an epitaxial growth process; and
forming metal source, drain and gate pads over the second confinement layer by lithographic processes to form the p-FET of which the active layer forms the p-channel;
wherein:
the first confinement layer is formed of a material or materials with a wider band gap than α-Sn, wherein the band gap offset between α-Sn and said material or materials allows confinement of charge carriers in the active layer so that the active layer acts as a quantum well, and
the second confinement layer is also formed of a material or materials with a wider band gap than α-Sn, wherein the band gap offset between α-Sn and said material or materials allows confinement of charge carriers in the active layer.
14. A method as claimed in claim 13 , where the step of preparing the substrate comprises preparing a surface substantially miscut to a crystal plane for subsequent growth of the first confinement layer, the active layer and the second confinement layer thereupon.
15. A method as claimed in claim 14 , wherein the substrate is GaAs or Si, and the crystal plane is the (001) plane.
16. A method as claimed in claim 13 , wherein any confinement layer is formed of Al x In 1-x Sb, wherein the value of x lies in the range 0≦x≦1.
17. A method as claimed in claim 16 , wherein the value of x lies in the range 0.30≦x≦0.45.
18. A method as claimed in claim 13 , wherein the growth conditions of the second confinement layer are controlled so as to prevent destabilisation of the active layer.