Video Transmission On A Serial Interface
A video transmission circuit for transmitting video data on a digital serial interface to a receive circuit arranged to process the video data at a constant rate, the circuit including a transmission block comprising: a packet generator arranged to generate, for each image of the video data, a plurality of packets, each containing a pixel group of the image; a transmit circuit arranged to transmit the packets of each image on a digital serial interface at time intervals based on the constant rate; and a synchronization circuit arranged to receive from the receive circuit, after transmission of a plurality of packets, a synchronization signal for synchronizing the beginning of the transmission of a next packet.
1 - 15 . (canceled)
16 . A video transmission circuit for transmitting video data on a digital serial interface to a receive circuit configured to process the video data at a constant rate, the circuit comprising a transmission block comprising:
a packet generator configured to generate, for each image of the video data, a plurality of packets, each containing a group of pixels of the image;
transmission circuitry configured to transmit the packets of each image over a digital serial interface at time intervals based on the constant rate; and
synchronization circuitry configured to receive from the receive circuit, after transmission of a plurality of packets, a synchronization signal for synchronizing the start of transmission of a next packet.
17 . The video transmission circuit of claim 16 , comprising a first timing control block configured to provide a first timing signal to said transmission circuitry, said time intervals being determined based on the first timing signal, and wherein said receive circuitry comprises a second timing control block configured to provide a second timing signal for controlling the timing of the video processing, the synchronization signal being generated based on the second timing signal.
18 . The video transmission circuit of claim 16 , wherein each group of pixels is a line of an image, and the packet generator is configured to generate packets, each of which comprises N lines of pixels, and wherein the transmission circuitry is configured to transmit the packets of each image over the digital serial interface at time intervals selected to correspond to N line periods, wherein N is an integer between 1 and M/2, M being the number of lines of each image.
19 . The video transmission circuit of claim 16 , further comprising a digital serial interface coupled to the transmission circuitry, and receive circuitry coupled to the digital serial interface for receiving said packets, the receive circuitry comprising a pixel buffer for temporarily storing said packets.
20 . The video transmission circuit of claim 19 , wherein the pixel buffer has a capacity smaller than or equal to an image of the video data.
21 . The video transmission circuit of claim 19 , wherein the receive circuitry comprises a video encoder.
22 . The video transmission circuit of claim 19 , wherein the receive circuitry comprises a hub coupled to a plurality of displays, the video trans-mission circuitry being configured to transmit video data to each of the displays, and further comprising an additional packet generator and additional transmission circuitry associated with each display.
23 . The video transmission circuit of claim 16 , wherein the synchronization circuitry is configured to transmit a synchronization request to the receive circuitry after transmission of a plurality of packets.
24 . The video transmission circuit of claim 16 , wherein the synchronization signal is a vertical synchronization signal for synchronizing the processing of the frames by the receive circuitry.
25 . An electronic device comprising:
a video transmission circuit and a memory coupled to said video transmission circuit;
said memory configured to store video data; and
said video transmission circuit comprising a transmission block comprising:
a packet generator configured to generate, for each image of the video data, a plurality of packets, each containing a group of pixels of the image;
transmission circuitry configured to transmit the packets of each image over a digital serial interface at time intervals based on the constant rate; and
synchronization circuitry configured to receive from the receive circuit, after transmission of a plurality of packets, a synchronization signal for synchronizing the start of transmission of a next packet.
26 . A method for transmitting video data over a digital serial interface to receive circuitry, the receive circuitry being configured to process the video data at a constant rate, the method comprising:
generating by a packet generator, for each image of the video data, a plurality of packets, each of which contains a group of pixels of the image;
transmitting by transmission circuitry the packets of each image on a digital serial interface at time intervals based on said constant rate; and
receiving from the receive circuitry, after transmission of a plurality of packets, a synchronization signal for synchronizing the start of transmission of a next packet.
27 . The method of claim 26 , wherein the start of transmission of the next packet is controlled to be equal to a configurable time delay after the transmission of the previous packet.
28 . The method of claim 26 , further comprising the storage by the receive circuitry of the received image data of said packets in a pixel buffer.
29 . The method of claim 26 , further comprising providing a first timing signal for synchronizing said time intervals and a second timing signal for controlling the timing of the video processing, the first timing signal being generated based on the second timing signal.
30 . The method of claim 26 , further comprising requesting said synchronization signal after transmission of each plurality of packets, and pausing the packet transmission until said synchronization signal is received.