High-efficiency solar cell structures and methods of manufacture
View Patent ↗Solar cells of varying composition are disclosed, generally including a central substrate, conductive layer(s), antireflection layers(s), passivation layer(s) and/or electrode(s). Multifunctional layers provide combined functions of passivation, transparency, sufficient conductivity for vertical carrier flow, the junction, and/or varying degrees of anti-reflectivity. Improved manufacturing methods including single-side CVD deposition processes and thermal treatment for layer formation and/or conversion are also disclosed.
1. A method of fabricating a solar cell, comprising;
providing a wafer as a central substrate;
depositing or growing at least one amorphous interface passivation layer over the substrate;
depositing at least one conductive and passivating layer on the at least one interface passivation layer, the at least one conductive and passivating layer comprising a dopant;
providing thermal treatment at a temperature of about 500° C. or higher, the thermal treatment crystallizing, at least in part, the at least one conductive and passivating layer and facilitating diffusion of the dopant from the at least one conductive and passivating layer through the at least one interface passivation layer; and
providing metallization as electrodes which directly contact the at least one conductive and passivating layer following the thermal treatment thereof, wherein the dopant diffused through the at least one interface passivation layer provides shortened charge carrier flow paths between the substrate and the electrodes through the at least one conductive and passivating layer and the at least one interface passivation layer.
2. The method of claim 1 , further comprising depositing at least one antireflective layer, and/or a low reflective index layer forming a good internal mirror on a back of the solar cell.
3. The method of claim 1 , wherein the depositing at least one interface passivation layer and the depositing at least one conductive and passivating layer comprises depositing an amorphous silicon-containing compound over the substrate and the providing thermal treatment of about 500° C. or higher separates the amorphous silicon-containing compound into the at least one interface passivation layer and the at least one conductive and passivating layer.
4. The method of claim 1 , wherein the thermal treatment results in perforation of the at least one interface passivation layer to allow carrier transport therethrough.
5. The method of claim 1 , wherein the at least one conductive and passivating layer comprises an amorphous, silicon containing compound, and wherein the thermal treatment initiates crystallization of the at least one conductive and passivating layer into a polycrystalline film.
6. The method of claim 1 , wherein the at least one conductive and passivating layer comprises an amorphous, silicon containing compound, and wherein the thermal treatment initiates crystallization of the at least one conductive and passivating layer and increases the optical transmissivity.
7. The method of claim 1 , wherein the at least one conductive and passivating layer comprises an amorphous, silicon containing compound, and wherein the thermal treatment activates doping atoms in the compound.
8. The method of claim 1 , wherein the at least one conductive and passivating layer comprises an amorphous, silicon containing compound, and wherein facilitating diffusion of the dopant further comprises facilitating diffusion of dopant atoms into the substrate to provide a high-low junction or a p-n junction.