Fabrication method for surrounding gate silicon nanowire transistor with air as spacers
The invention discloses a fabrication method for a surrounding gate silicon nanowire transistor with air as spacers. The method comprises: performing isolation, and depositing a material A which has a higher etch selectivity ratio with respect to Si; performing photolithography to define a Fin hard mask; etching the material A to form the Fin hard mask; performing source and drain implantation; performing photolithography to define a channel region and large source/drain regions; forming the Si Fin and the large source/drains; removing the hard mask of the material A; forming a nanowire; etching the SiO 2 to form a floating nanowire; forming a gate oxide layer; depositing a polysilicon; performing polysilicon injection; performing annealing to activate dopants; etching the polysilicon; depositing SiN; performing photolithography to define a gate pattern; etching the SiN and the polysilicon to form the gate pattern; separating the gate and the source/drain with a space in between filled with air; depositing SiO 2 to form air sidewalls; performing annealing to densify the SiO 2 layer; using subsequent processes to complete the device fabrication. The invention is compatible with the CMOS process flow. The introduction of the air sidewalls can effectively reduce the parasitic capacitance of the device, and improve the transient response of the device, so that the method is applicable for a logic circuit with high performance.
1. A fabrication method for a surrounding gate silicon nanowire transistor with air as spacers, characterized in that, the transistor is fabricated on a SOI substrate, and the method comprises the following steps:
performing an isolation process on the SOI substrate;
depositing a material A having a relatively high etching selectivity ratio with respect to Si on the SOI substrate, the SOI substrate including Silicon;
performing photolithography on material A to define a Fin hard mask, the performing photolithography creating a pattern of photoresist;
etching the material A and transferring the pattern of photoresist onto the material A to form the Fin hard mask;
performing source and drain implantation on the SOI substrate;
performing photolithography to define a channel region and source/drain large regions on the silicon of the SOI substrate;
etching the silicon by using the pattern of photoresist and the Fin hard mask of the material A as barriers, so as to form the Fin and the large source/drains within the silicon;
removing the hard mask of the material A from the Si on the SOI substrate;
performing oxidization of the silicon on the SOI substrate to form a nanowire;
etching the the oxidized silicon through isotropic wet etching to form a floating nanowire;
forming a gate oxide layer on a gate of the Si on the SOI substrate;
depositing a polysilicon on the silicon of the SOI substrate, including on the large source/drain;
performing polysilicon implantation;
performing annealing to activate dopants of the polysilicon;
etching the polysilicon until a polysilicon thickness of the polysilicon on the source/drain is around 30 to 50 nm;
depositing SiN on to the polysilicon;
performing photolithography to define a gate pattern on the SiN;
etching the SiN and the polysilicon and transferring a second pattern of the photoresist onto the polysilicon to form the gate pattern;
etching the polysilicon through isotropic dry etching or isotropic wet etching, to separate the gate and the source/drain with a space in between filled with air;
depositing SiO 2 on to the SiN and polysilicon to form air sidewalls;
performing annealing to densify the SiO 2 layer;
using CMOS backend processes to complete the device fabrication.
2. The fabrication method of claim 1 , characterized in that, performing the isolation process comprises performing a silicon island isolation or a local oxidation of silicon.
3. The fabrication method of claim 1 , characterized in that, etching the material A, the silicon, the polysilicon, the SiN and the polysilicon comprises etching the material A, the silicon, the polysilicon, the SiN and the polysilicon by using an anisotropic dry etching technology.
4. The fabrication method of claim 1 , characterized in that, performing source and drain implantation comprising performing an implantation with an angle of 0 degree.
5. The fabrication method of claim 1 , characterized in that, removing the hard mask of the material A comprises removing the SiN by a concentrated phosphoric acid at 170° C.
6. The fabrication method of claim 1 , characterized in that performing oxidization comprises performing a dry oxidation or a wet oxidation.
7. The fabrication method of claim 1 , characterized in that the oxidized silicon is removed by using a hydrofluoric acid.
8. The fabrication method as in claim 1 , characterized in that, forming the gate oxide layer comprises forming a silicon dioxide layer dielectric layer by a dry oxidation, or other dielectric layer with a high dielectric constant.
9. The fabrication method as in claim 1 , characterized in that, depositing the material A, the polysilicon, SiN, SiO 2 comprises depositing the material A, the polysilicon, SiN, SiO 2 by using a chemical vapor deposition method.