IP Library Granted Patent US 9,137,880
Granted Patent B2
US 9,137,880 · App. 13/267,819 · Granted Sep 15, 2015

Generation from phase cut dimmer output with fast response to changes in dimmer position

Inventors: Bobby Jacob Daniel (Eindhoven, NL); Hinderikus Maria Wilhelmus Langeslag (Wijchen, NL)
Assignee: NXP B.V.
H05B39/08H05B33/0815H05B33/0863Y02B20/346
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Quick Facts
Patent No.
US 9,137,880
App. No.
13/267,819
Granted
Sep 15, 2015
Kind
B2
Abstract

A circuit for a dimmer system is disclosed, in which a phase-cut dimmer output signal is converted to a dimming control level signal. The phase-cut dimmer output signal is used to generated a pulse modulated signal indicative of the duty cycle of the phase cut dimmer output signal, and the pulse modulated signal is directly converted to a piece-wise linear dimming control level signal. By directly converting the pulse modulated signal to a piece-wise linear dimming control level signal, no further processing is necessary to produce a dimming signal which closely resembles the ideal logarithmic response of the human eye. A corresponding method for a dimmer system is also disclosed, as is a dimmer system.

Claims (27)

1. A circuit for a dimming system, the circuit comprising:

an input for receiving a phase-cut dimmer output signal, the phase-cut dimmer output signal having a period and complementary cut and un-cut parts;

an output for outputting a dimming control level signal;

a comparator, connected to the input and arranged to produce a pulse-modulated signal from the phase-cut dimmer output signal, the pulse-modulated signal having an on-time which varies in dependence on the duration of the un-cut part; and

a converter configured to determine the dimming level control signal directly from the pulse-modulated signal, such that the dimming level control signal has a non-linear but piece-wise linear relationship with the un-cut part; and

wherein the converter is configured to determine the dimming level control signal by means of a variable frequency clock which increments or decrements a counter at each clock cycle during the on-time, and to determine the dimming level control signal from the counter.

2. A circuit according to claim 1 , wherein the clock is arranged to run at an initial rate during an initial part of the period which initial rate is in a fixed relationship with a base rate, and when the counter reaches a predetermined number, to terminate the initial part, set a flag, and reset the counter; the circuit being further configured to set the dimming control level signal to a fully dimmed level if the flag is not set.

3. A circuit according to claim 1 , wherein the clock is arranged to run at a first rate over a first part of the period and at a second rate over a second part of the period, wherein the first rate is in a fixed relationship with a base rate and the second rate in a fixed relationship with and higher than the first rate and the second part of the period is later in the period than the first part of the period.

4. A circuit according to claim 2 , wherein the clock is arranged to run at an initial rate during an initial part of the period which precedes both the first part and the second part in the period, and when the counter reaches a predetermined number, to terminate the initial part, set a flag, and reset the counter; the circuit being further configured to set the dimming control level signal to a fully dimmed level if the flag is not set.

5. A circuit according to claim 2 , further configured to operate a calibration phase in which the base rate is adjusted upwards period-by-period in response to the counter not reaching a second predetermined number during a period or the base rate is adjusted downwards period-by-period in response to the counter exceeding the second predetermined number during the period respectively.

6. A circuit according to claim 2 , further configured to operate a calibration phase in which the base rate is adjusted downwards period-by-period in response to the counter reaching a second predetermined number before the end of a period.

7. A controller for a dimmable lighting system comprising a phase-cut dimmer and a circuit as claimed in claim 1 .

8. A method of determining a dimming control level from a phase-cut dimmer output signal having a period and complementary cut and un-cut parts, the method comprising

determining a pulse-modulated signal from the phase-cut dimmer output signal, the pulse-modulated signal having an on-time which varies in dependence on the duration of the un-cut part; and

determining the dimming control level signal directly from the pulse modulated signal such that the dimming control level has a nonlinear piece-wise linear relationship with the cut part; and

wherein determining the dimming control level signal directly from the pulse modulated signal comprises

incrementing a counter of a variable frequency clock at each clock cycle during the on-time, and

determining the dimming level control signal from the counter.

9. The method of claim 8 , further comprising running the clock at an initial rate during an initial part of the period which initial rate is in a fixed relationship with a base rate,

and when the counter reaches a predetermined number, terminating the initial part, setting a flag, and resetting the counter;

and setting the dimming control level signal to a fully dimmed level if the flag is not set.

10. The method of claim 9 , further comprising running the clock at a first rate over a first part of the period and at a second rate over a second part of the period, wherein the first rate is in a fixed relationship with a base rate and the second rate in a fixed relationship with and higher than the first rate and the second part of the period is later in the period than the first part of the period.

11. The method of claim 10 , further comprising running the clock at an initial rate during an initial part of the period which precedes both the first part and the second part in the period,

and when the counter reaches a predetermined number, terminating the initial part, setting a flag, and resetting the counter;

and setting the dimming control level signal to a fully dimmed level if the flag is not set.

12. The method of any of claim 8 , further comprising operating a calibration phase in which the base rate is adjusted upwards period-by-period, in response to the counter not reaching a second predetermined number during a period or the base rate is adjusted downwards period-by-period in response to the counter exceeding the second predetermined number during the period respectively.

13. The method of claim 8 , further configured to operate a calibration phase in which the base rate is adjusted downwards period-by-period in response to the counter reaching a second predetermined number before the end of a period.

Assignments (14)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2020
From: SILERGY CORP.
To: SILERGY SEMICONDUCTOR (HONG KONG) LTD.
Reel/Frame 054751/0138 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
PATENT RELEASE Recorded Jun 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039070/0577 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2016
From: NXP B.V.
To: SILERGY CORP.
Reel/Frame 038304/0168 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2012
From: DANIEL, BOBBY JACOB; LANGESLAG, WILHELMUS HINKERIKUS MARIA
To: NXP B.V.
Reel/Frame 029220/0935 →
Priority Claims (1)
EP 10186908 · Oct 7, 2010 · regional
Continuity (1)
Related Publication 20120086354A1 · Apr 12, 2012