Building, transmitting, and receiving frame structures in power line communications
Systems and methods for building, transmitting, and receiving frame structures in power line communications (PLC) are described. Various techniques described herein provide a preamble design using one or more symbols based on a chirp signal that yields a low peak-to-average power ratio (PAPR). According to some techniques, the preamble may be constructed with one or more different types and/or number of symbols configured to identify a PLC domain operating in close physical proximity to another PLC domain. According to other techniques, one or more preamble symbols may be interspersed within a header portion of a PLC frame to facilitate estimation of a frame boundary and/or sampling frequency offset, for example, in the presence of impulsive noise. According to yet other techniques, a PLC detector may be capable of receiving and decoding two or more types of PLC frames (e.g., using different PLC standards).
1. A computing device comprising:
a processor; and
a memory coupled to the processor, wherein the memory is configured to store program instructions, and wherein the program instructions are executable by the processor to cause the computing device to:
generate a chirp sequence having a bandwidth selected, at least in part, by subtracting an excess bandwidth parameter from a low nominal frequency and adding the excess bandwidth parameter to a high nominal frequency;
extract a phase angle of a frequency-domain version of the chirp sequence to obtain a flattened frequency spectrum;
create a phase quantized sequence based, at least in part, upon the flattened frequency spectrum;
employ the phased quantized sequence as a symbol to generate a power line communication (PLC) preamble portion of a PLC frame;
repeat the symbol N 1 times to create a first section of the PLC preamble portion, where N 1 is an integer;
repeat a phase inverted version of the symbol N 2 times to create a second section of the PLC preamble portion, where N 2 is an integer different from N 1 ;
extend the first and second sections of the PLC preamble portion; and
combine the first and second extended sections of the PLC preamble portion.
2. The computing device of claim 1 , wherein the high and low nominal frequencies are based, at least in part, upon a PLC standard, and wherein the excess bandwidth parameter is a function of a difference between the high and low nominal frequencies.
3. The computing device of claim 1 , wherein to create the phase quantized sequence, the program instructions are executable by the processor to further cause the computing device to use a quantization factor smaller than another quantization factor selected based, at least in part, upon a PLC standard.
4. The computing device of claim 1 , wherein to extend the first and second sections of the PLC preamble portion, the program instructions are executable by the processor to further cause the computing device to:
prepend last β samples of the symbol to a first symbol of the first section of the PLC preamble portion and append first β samples of the symbol to a last symbol of the first section of the PLC preamble portion to create the first extended section of the PLC preamble portion, where β is less than a number of samples in the symbol;
window the first and last β samples of the first extended section of the PLC preamble portion;
prepend the last β samples of the symbol to a first symbol of the second section of the PLC preamble portion and append the first β samples of the symbol to a last symbol of the second section of the PLC preamble portion to create second extended section of the PLC preamble portion; and
window the first and last β samples of the second extended section of the PLC preamble portion.
5. The computing device of claim 1 , wherein β is half the number of samples in the symbol, and wherein N 1 identifies a given PLC domain.
6. A computing device comprising:
a processor; and
a memory coupled to the processor, wherein the memory is configured to store program instructions, and wherein the program instructions are executable by the processor to cause the computing device to:
generate a chirp sequence having a bandwidth selected, at least in part, by subtracting an excess bandwidth parameter from a low nominal frequency and adding the excess bandwidth parameter to a high nominal frequency;
extract a phase angle of a frequency-domain version of the chirp sequence to obtain a flattened frequency spectrum;
create a phase quantized sequence based, at least in part, upon the flattened frequency spectrum;
employ the phased quantized sequence as a symbol to generate a power line communication (PLC) preamble portion of a PLC frame;
repeat the symbol N 1 times to create a first section of the PLC preamble portion, where N 1 is an integer;
generate another sequence independent from than the phased quantized sequence of the symbol;
repeat the another sequence N 2 times to create a second section of the PLC preamble portion, where N 2 is an integer; and
combine the first and second sections of the PLC preamble portion.
7. The computing device of claim 6 , wherein the another sequence includes a Zadoff-Chu sequence.
8. The computing device of claim 6 , wherein the another sequence identifies a given PLC domain.
9. The computing device of claim 6 , wherein N 1 and the another sequence in combination identify a given PLC domain.
10. A computing device comprising:
a processor; and
a memory coupled to the processor, wherein the memory is configured to store program instructions, and wherein the program instructions are executable by the processor to cause the computing device to:
generate a chirp sequence having a bandwidth selected, at least in part, by subtracting an excess bandwidth parameter from a low nominal frequency and adding the excess bandwidth parameter to a high nominal frequency;
extract a phase angle of a frequency-domain version of the chirp sequence to obtain a flattened frequency spectrum;
create a phase quantized sequence based, at least in part, upon the flattened frequency spectrum;
employ the phased quantized sequence as a symbol to generate a power line communication (PLC) preamble portion of a PLC frame;
identify the symbol within the PLC preamble portion of the PLC frame;
insert an instance of the symbol at a predetermined location within a PLC header portion of the PLC frame; and
cause the PLC frame to be transmitted over a power line.
11. A computing device comprising:
a processor; and
a memory coupled to the processor, wherein the memory is configured to store program instructions, and wherein the program instructions are executable by the processor to cause the computing device to:
generate a chirp sequence having a bandwidth selected, at least in part, by subtracting an excess bandwidth parameter from a low nominal frequency and adding the excess bandwidth parameter to a high nominal frequency;
extract a phase angle of a frequency-domain version of the chirp sequence to obtain a flattened frequency spectrum;
create a phase quantized sequence based, at least in part, upon the flattened frequency spectrum;
employ the phased quantized sequence as a symbol to generate a power line communication (PLC) preamble portion of a PLC frame;
receive another PLC frame;
in response to a determination that the computing device is operating in a multi-preamble decode mode,
attempt to decode a preamble portion of the another PLC frame using a first decoding technique, the preamble portion following one of a plurality of different PLC standards;
in response to the attempt being successful, decode the another PLC frame using the first decoding technique; and
in response to the attempt being unsuccessful, attempt to decode the preamble portion of the another PLC frame using a second decoding technique, the first and second decoding techniques each based upon a different PLC standard.