Method and apparatus for determining duty cycle of a clock in a circuit using a configurable phase locked loop

1. A method comprising:

phase shifting a second clock signal by a phase increment with respect to a first clock signal, wherein the first clock signal and the second clock signal have the same periods;

sampling the first clock signal with the second clock signal, wherein the output of the sample indicates whether the sample of the first clock signal is at a logic one state or a logic zero state;

incrementing a count of logic one samples if the sample of the first clock signal is at a logic one state; and

repetitively performing the process of phase shifting the second clock signal and sampling the first clock signal.

2. The method of claim 1 , wherein the second clock signal is derived from the first clock signal.

3. The method of claim 1 , wherein the process of repetitively phase shifting the second clock signal and sampling the first clock signal occurs until the second clock signal has been phase shifted by a determined number of the phase increments.

4. The method of claim 3 wherein the determined number of the phase increments is a multiple of an integer portion of a quotient yielded by dividing 360 by the phase increment or a multiple of a quotient yielded by dividing 360 by the phase increment.

5. The method of claim 1 , wherein the process of repetitively phase shifting the second clock signal and sampling the first clock signal occurs until at least the sampling indicates that the first clock signal is at a logic zero state.

6. The method of claim 1 , wherein a state machine is used to generate commands used in the phase shifting and the sampling.

7. The method of claim 1 , wherein the sampling is done with a rising edge of the second clock signal.

8. The method of claim 1 , comprising determining a duty cycle of the first clock signal by dividing the count of logic one samples by a number of phase increments in a period of the first clock cycle.

9. A system comprising:

a phase shifting circuitry configured to phase shift a second clock signal by a phase increment with respect to a first clock signal, wherein the first clock signal and the second clock signal have the same periods;

a sampling circuitry configured to sample the first clock signal with the second clock signal, wherein the output of the sampling circuitry indicates whether the sample of the first clock signal is at a logic one state or a logic zero state;

a counting circuitry that is configured to increment a count of logic one samples if the sample of the first clock signal is at a logic one state; and

a control circuitry configured to control at least the phase shifting circuitry and the sampling circuitry to repetitively perform the process of phase shifting the second clock signal and sampling the first clock signal.

10. The system of claim 9 , wherein the second clock signal is derived from the first clock signal.

11. The system of claim 9 , wherein the process of repetitively phase shifting the second clock signal and sampling the first clock signal occurs until the phase shifting circuitry has phase shifted the second clock signal by a determined number of the phase increments.

12. The system of claim 11 , wherein the determined number of the phase increments is a multiple of an integer portion of a quotient yielded by dividing 360 by the phase increment or a multiple of a quotient yielded by dividing 360 by the phase increment.

13. The system of claim 9 , wherein the process of repetitively phase shifting the second clock signal and sampling the first clock signal occurs until at least the sampling indicates that the first clock signal is at a logic zero state.

14. The system of claim 9 , wherein the phase shifting circuitry is one of:

a phase locked loop and a digital delay locked loop.

15. The system of claim 9 , wherein the sampling circuitry comprises an edge triggered flip-flop.

16. The system of claim 9 , wherein the control circuitry is a state machine.

17. The system of claim 9 , wherein the sampling is done with a rising edge of the second clock signal.

18. The system of claim 9 , comprising a processor enabled to determine a duty cycle of the first clock signal by dividing the count of logic one samples by a number of phase increments in a period of the first clock cycle.

19. A method comprising:

adjusting a phase of a second clock signal by a phase increment with respect to a first clock signal, wherein the second clock signal is derived from the first clock signal and has the same period as the first clock signal;

sampling the first clock signal with the second clock signal;

determining whether a sample of the first clock signal is a logic one or a logic zero;

incrementing a counter if the sample is at a logic one state to update a count of logic one samples;

determining whether the phase of the second clock signal has been adjusted a maximum number of times; and

performing the process of adjusting the phase of the second clock signal and sampling the first clock signal if the phase of the second clock signal has not been adjusted by the phase increment a maximum number of times.

20. The method of claim 19 , wherein the maximum number of times is a multiple of an integer portion of a quotient yielded by dividing 360 by the phase increment or a multiple of a quotient yielded by dividing 360 by the phase increment.

21. The method of claim 19 , wherein the maximum number of times is reached when the sampling indicates that the first clock signal is at a logic zero state.

22. The method of claim 19 , comprising determining a duty cycle of the first clock signal by dividing the count of the logic one samples by a number of phase increments in a period of the first clock cycle.