Copper Stud Bump Wafer Level Package
There is provided a system and method for a copper stud bump wafer level package. There is provided a semiconductor package comprising a semiconductor die having a plurality of bond pads on an top surface thereof, a plurality of metallic stud bumps mechanically and electrically coupled to said plurality of bond pads, and a plurality of solder balls mechanically and electrically coupled to said plurality of metallic stud bumps. Advantageously, the metallic stud bumps may be provided using standard wirebonding equipment, avoiding the conventional wafer level package requirement for photolithography and deposition steps to provide a multi-layer metallic routing structure. As a result, reduced cycle times, lower cost, and reduced complexity may be provided. Alternative fabrication processes utilizing metallic stud bumps may also support multi-die packages with dies from different wafers and packages with die perimeter pads wirebonded to substrates.
1 . A semiconductor package comprising:
a semiconductor die having a plurality of bond pads on an top surface thereof;
a plurality of metallic stud bumps mechanically and electrically coupled to said plurality of bond pads;
a plurality of solder balls mechanically and electrically coupled to said plurality of metallic stud bumps.
2 . The semiconductor package of claim 1 , wherein said plurality of metallic stud bumps is a plurality of copper stud bumps.
3 . The semiconductor package of claim 1 , further comprising a mold compound encapsulating said plurality of metallic stud bumps while exposing a top surface of each of said plurality of metallic stud bumps.
4 . The semiconductor package of claim 1 , wherein said plurality of bond pads include a single metal finish.
5 . The semiconductor package of claim 4 , wherein said single metal finish is an aluminum finish.
6 . The semiconductor package of claim 1 , wherein said semiconductor die is mounted on a substrate.
7 . The semiconductor package of claim 6 , wherein said semiconductor die further includes a plurality of die perimeter pads on said top surface thereof, said plurality of die perimeter pads connecting to said substrate by a plurality of wire bonds.
8 . The semiconductor package of claim 7 , wherein said plurality of wire bonds is a plurality of copper wire bonds.
9 . The semiconductor package of claim 6 , wherein another semiconductor die is mounted on said substrate, said another semiconductor die having a plurality of bond pads on an top surface thereof, said another semiconductor die having a plurality of metallic stud bumps mechanically and electrically coupled to said plurality of bond pads, said another semiconductor die having and a plurality of solder balls mechanically and electrically coupled to said plurality of metallic stud bumps.
10 . The semiconductor package of claim 9 , wherein a process feature size of said semiconductor die is different from a process feature size of said another semiconductor die.
11 . A method for fabricating a semiconductor package comprising:
forming a wafer including a semiconductor die having a plurality of bond pads on an top surface thereof;
ball bonding and terminating a plurality of bond wires to each of said plurality of bond pads, thereby forming a plurality of metallic stud bumps mechanically and electrically coupled to said plurality of bond pads;
leveling a top surface of each said plurality of metallic stud bumps;
bumping said plurality of metallic stud bumps with a plurality of solder balls;
singulating said semiconductor die from said wafer.
12 . The method of claim 11 , wherein after said forming said wafer and prior to said singulating, no photolithography or deposition equipment is utilized.
13 . The method of claim 11 further comprising, prior to said leveling:
applying a grinding tape to a backside of said wafer.
14 . The method of claim 11 , wherein said leveling comprises:
encapsulating a mold compound around said wafer including said plurality of metallic stud bumps;
grinding said mold compound to expose a top surface of each of said plurality of metallic stud bumps through said mold compound.
15 . The method of claim 11 , wherein said leveling comprises:
encapsulating a mold compound around said wafer including said plurality of metallic stud bumps while exposing a top surface of each of said plurality of metallic stud bumps;
tamping said plurality of metallic stud bumps.
16 . The method of claim 11 further comprising, prior to said singulating, verifying a proper functionality of said semiconductor die by a wafer probe test applied to said plurality of solder balls.
17 . The method of claim 11 further comprising, prior to said singulating, laser marking said semiconductor die.
18 . The method of claim 11 further comprising, prior to said singulating, back grinding said semiconductor die to a specific thickness.
19 . The method of claim 11 wherein said plurality of metallic stud bumps is a plurality of copper stud bumps.
20 . The method of claim 11 wherein said plurality of bond pads include a single metal finish.