Electrophoretic display device and method of fabricating the same
View Patent ↗A method of fabricating an electrophoretic display device includes forming a gate line along a direction, a gate electrode extending from the gate line, a common line parallel to the gate line, and a first storage electrode extending from the common line on a substrate, forming a gate insulating layer on an entire surface of the substrate including the gate line, the gate electrode, the common line and the first storage electrode, forming a semiconductor layer, a data line, and source and drain electrodes through a mask process, wherein the semiconductor layer is disposed over the gate electrode, the data line crosses the gate line to define a pixel region, the source electrode extends from the data line, and the drain electrode is spaced apart from the source electrode over the semiconductor layer.
1. A method of fabricating an electrophoretic display device, comprising:
forming a gate line along a direction, a gate electrode extending from the gate line, a common line parallel to the gate line, and a first storage electrode extending from the common line on a substrate;
forming a gate insulating layer on an entire surface of the substrate including the gate line, the gate electrode, the common line and the first storage electrode;
forming a semiconductor layer, a data line, and source and drain electrodes through a mask process, wherein the semiconductor layer is disposed over the gate electrode, the data line crosses the gate line to define a pixel region, the source electrode extends from the data line, and the drain electrode is spaced apart from the source electrode over the semiconductor layer, wherein the gate electrode, the semiconductor layer, the source electrode and the drain electrode constitute a thin film transistor;
forming a first passivation layer over the gate line, the data line and the thin film transistor, wherein the first passivation layer partially exposes the drain electrode; and
forming a pixel electrode on the first passivation layer, wherein the pixel electrode contacts the drain electrode and overlaps the gate line and the data line, wherein the pixel electrode includes a second storage electrode overlapping the first storage electrode, and the first and second storage electrodes form a storage capacitor with the gate insulating layer interposed therebetween.
2. The method according to claim 1 , wherein the first passivation layer is formed of an organic insulating material.
3. The method according to claim 1 , wherein the pixel electrode is formed of a transparent conductive material.
4. The method according to claim 1 , wherein the pixel electrode has a size corresponding to substantially the entire portion of the pixel region.
5. The method according to claim 1 , wherein the mask process includes a diffraction exposure method or a halftone exposure method using a mask, which includes a light-transmitting portion, a half light-transmitting portion and a light-blocking portion.
6. The method according to claim 1 , further comprising forming a second passivation layer covering the thin film transistor and the data line before forming the first passivation layer, wherein the second passivation layer is formed of an inorganic insulating material and includes a drain contact hole exposing the drain electrode.
7. The method according to claim 6 , wherein the first and second storage electrodes form the storage capacitor with the gate insulating layer and the second passivation layer interposed therebetween.
8. The method according to claim 1 , wherein forming the first passivation layer includes:
forming an organic insulating material layer on an entire surface of the substrate including the second passivation layer;
exposing the organic insulating material layer to light using a diffraction exposure method or a halftone exposure method and developing the organic insulating material, thereby forming a first organic insulating pattern, a second organic insulating pattern and a through hole, wherein the through hole exposes the second passivation layer over the drain electrode, wherein the first organic insulating pattern has a first thickness and corresponds to the gate line, the data line and the thin film transistor, wherein the second organic insulating pattern has a second thickness less than the first thickness and corresponds to the pixel region;
forming the drain contact hole by selectively removing the second passivation layer; and
forming the first passivation layer having a third thickness by completely removing the second organic insulating pattern and partially removing the first organic insulating pattern.
9. The method according to claim 1 , wherein forming the first passivation layer uses a dry-etching method.
10. The method according to claim 1 , further comprising forming a third passivation layer on the first passivation layer before forming the pixel electrode, wherein the third passivation layer is formed of an inorganic insulating material.
11. The method according to claim 1 , wherein the first passivation layer has a thickness of about 2 μm to about 4 μm.
12. The method according to claim 1 , further comprising attaching an electrophoresis film including an adhesive layer, an ink layer having a charged particle, a common electrode and a base film onto the pixel electrode, the ink layer disposed between the adhesive layer and the base film, the adhesive layer being on the pixel electrode, the charged particle including a negatively-charged sub-particle having a white color and a positively-charged sub-particle having a black color.