Electronic circuit with a floating gate transistor and a method for deactivating a floating gate transistor temporarily
View Patent ↗An electronic circuit includes a floating gate transistor with a floating gate capacitor. The floating gate transistor can be programmed to be in an ON or an OFF state by charging the floating gate capacitor. The circuit further includes a deactivation capacitor adapted to store a charge sufficient for deactivating the floating gate transistor temporarily. The deactivation capacitor is connectable in series to the floating gate capacitor. A method for deactivating a floating gate transistor temporarily is provided, wherein the floating gate transistor includes a floating gate capacitor. A deactivation capacitor is charged with a charge sufficient for changing the state of the floating gate transistor temporarily. The deactivation capacitor is connected in series to the floating gate capacitor for deactivating the floating gate transistor.
1. An electronic circuit, comprising:
a floating gate transistor with a floating gate capacitor, wherein the floating gate transistor can be programmed to be in an ON or an OFF state by charging the floating gate capacitor;
a deactivation capacitor adapted to store a charge sufficient for deactivating the floating gate transistor temporarily, the deactivation capacitor being connectable in series to the floating gate capacitor.
2. The circuit of claim 1 , wherein
the deactivation capacitor is connected with a first terminal to a first terminal of the floating gate capacitor; the circuit further comprising
a first switch connected between the first terminal of the deactivation capacitor and ground;
a second switch connected between a second terminal of the deactivation capacitor and ground;
a third switch connected between the second terminal of the deactivation capacitor and a supply voltage, wherein
the switches are controlled to be in a charge position with the first and third switches closed and the second switch open during a first time interval, and to be in a deactivating position with the first and third switches open and the second switch closed during a second time interval.
3. The circuit of claim 2 , further comprising:
a fourth switch coupled to connect a second terminal of the floating gate capacitor either to a programming voltage or to ground, the programming voltage being higher than the supply voltage, wherein the switches are controlled to be in a first programming position with the first switch closed, the second and third switches open and the fourth switch switched to the programming voltage during a third time interval.
4. The circuit of claim 3 , further comprising:
a fifth switch connected between the first terminal of the floating gate capacitor and the programming voltage, wherein the switches are controlled to be in a second programming position with the first, the second and third switches open, the fourth switch switched to ground and the fifth switch closed during a fourth time interval.
5. The circuit of claim 4 , wherein
the floating gate transistor is an N-channel MOS field effect transistor of an enhancement type; and
the first switch comprises two anti-serial connected N-channel MOS field effect transistors of an enhancement type.
6. The circuit of claim 5 wherein the second switch comprises an N-channel MOS field effect transistor of an enhancement type and the third switch comprises a P-channel MOS field effect transistor of an enhancement type, the gates of the transistors of the second and the third switch being interconnected.
7. The circuit of claim 3 , wherein
the floating gate transistor is an N-channel MOS field effect transistor of an enhancement type; and
the first switch comprises two anti-serial connected N-channel MOS field effect transistors of an enhancement type.
8. The circuit of claim 7 , wherein the second switch comprises an N-channel MOS field effect transistor of an enhancement type and the third switch comprises a P-channel MOS field effect transistor of an enhancement type, the gates of the transistors of the second and the third switch being interconnected.
9. The circuit of claim 2 , wherein
the floating gate transistor is an N-channel MOS field effect transistor of an enhancement type; and
the first switch comprises two anti-serial connected N-channel MOS field effect transistors of an enhancement type.
10. The circuit of claim 9 , wherein the second switch comprises an N-channel MOS field effect transistor of an enhancement type and the third switch comprises a P-channel MOS field effect transistor of an enhancement type, the gates of the transistors of the second and the third switch being interconnected.
11. The circuit of claim 10 , wherein the circuit is an integrated CMOS circuit.
12. A passive transponder comprising the circuit of claim 11 .
13. A method for deactivating a floating gate transistor temporarily, wherein the floating gate transistor comprises a floating gate capacitor, the method comprising:
charging a deactivation capacitor with a charge sufficient for changing the state of the floating gate transistor temporarily;
connecting the deactivation capacitor in series to the floating gate capacitor for deactivating the floating gate transistor.
14. The method of claim 13 , further comprising:
charging the deactivation capacitor during a first time interval by closing a first switch which is connected between a first terminal of the deactivation capacitor and ground;
opening a second switch which is connected between a second terminal of the deactivation capacitor and ground;
closing a third switch which is connected between a second terminal of the deactivation capacitor and a supply voltage; and
deactivating the floating gate transistor temporarily during a second time interval by opening the first switch;
closing the second switch; and
opening the third switch.