SOI-based CMUT device with buried electrodes
A multi-layer stacked micro-electro-mechanical (MEMS) device that acts as a capacitive micromachined ultrasonic transducer (CMUT) with a hermetically sealed device cavity formed by a wafer bonding process with semiconductor and insulator layers. The CMUT design uses a doped Si SOI and wafer bonding fabrication method, and is composed of semiconductor layers, insulator layers, and metal layers. Conventional doped silicon may be used for electrode layers. Other suitable semi-conductor materials such as silicon carbide may be used for the electrode layers. The insulator may be silicon oxide, silicon nitride or other suitable dielectric.
1. A capacitive micromachined ultrasonic transducer (CMUT) device, comprising:
a wafer having at least a first semi-conductor electrode layer on an insulating dielectric;
the first semi-conductor electrode layer forming a CMUT pattern with dielectric stand-offs on the first semi-conductor electrode layer, the dielectric stand-offs being continuous in at least selected portions of the CMUT pattern to define sealed CMUT cavities;
a second semi-conductor electrode layer bonded onto the dielectric stand-offs with a gap between the first semi-conductor electrode layer and the second semi-conductor electrode layer creating the sealed CMUT cavities, the second semi-condutor electrode layer comprising a mechanical membrane responsive to an electrical stimulus to generate an ultrasonic signal and responsive to sound waves to change capacitance;
the dielectric stand-offs having a height sufficient to provide electrical isolation between the first semi-conductor electrode layer and the second semi-conductor electrode layer; and
for each CMUT in the CMUT pattern, respective contacts on the first semi-conductor electrode layer and the second semi-conductor electrode layer.
2. The CMUT of claim 1 in which the respective contacts comprise metalized portions of the respective first semi-conductor electrode layer and the second semi-conductor electrode layer.
3. The CMUT of claim 2 in which a portion of the second semi-conductor electrode layer is removed to provide access to the respective contact on the first semi-conductor electrode layer.
4. The CMUT of claim 2 in which the wafer comprises a handle layer having a porton removed.
5. The CMUT of claim 1 further comprising a barrier dielectric on the CMUT pattern of the wafer.
6. The CMUT of claim 1 in which the semi-conductor comprises silicon or silicon carbide.
7. The CMUT of claim 1 in which the dielectric comprises one or more oxides, nitrides or oxynitrides.
8. The CMUT of claim 1 in which the dielectric is one or more of a silicon oxide, a silicon nitride and a silicon oxynitride.
9. The CMUT of claim 1 in which the second semi-conductor electrode layer comprises a common electrode.
10. The CMUT of claim 1 in which the first semi-conductor electrode layer comprises a second mechanical membrane.