IP Library Granted Patent US 8,927,416
Granted Patent B2
US 8,927,416 · App. 13/274,039 · Granted Jan 6, 2015

Semiconductor device and method of manufacturing the same

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Quick Facts
Patent No.
US 8,927,416
App. No.
13/274,039
Granted
Jan 6, 2015
Kind
B2
Abstract

A first insulating film is formed on a semiconductor substrate, an interconnect groove is formed in the first insulating film, the inside of the interconnect groove is filled with a metal film, thereby forming a first interconnect. Then, a protective film is formed on the first insulating film and the first interconnect, and the surface of the protective film is exposed to reactive gas, thereby forming a reaction layer on an interface between the first interconnect and the protective film.

Claims (48)

1. A method of manufacturing a semiconductor device, the method comprising the steps of:

(a) forming a first insulating film on a semiconductor substrate;

(b) forming an interconnect groove in the first insulating film;

(c) forming a first interconnect in the interconnect groove;

(d) forming a protective film on the first insulating film and the first interconnect; and

after the step (d), (e) exposing a surface of the protective film to reactive gas, thereby forming a reaction layer on an interface between the first interconnect and the protective film.

2. The method of claim 1 , wherein

the step (e) is performed by exposing the surface of the protective film to a silicon compound or a germanium compound.

3. The method of claim 1 , wherein

the step (e) includes a sub-step of chemically activating the reactive gas.

4. The method of claim 1 , wherein

the step (e) includes a sub-step of chemically activating the reactive gas by ionizing the reactive gas.

5. The method of claim 1 , wherein

the step (e) includes a sub-step of physically activating the reactive gas.

6. The method of claim 1 , wherein

the step (e) includes a sub-step of physically activating the reactive gas by imparting kinetic energy to the reactive gas.

7. The method of claim 1 , further comprising the steps of:

(f) forming a second insulating film on the protective film;

(g) forming a via hole inside the second insulating film; and

(h) filling the via hole with a metal material to form a via, and forming a second interconnect so that the second interconnect is connected to the via.

8. The method of claim 1 , wherein

the protective film is a silicon carbonitride film.

9. The method of claim 1 , further comprising the step of

(c1) forming a cover layer in the upper part of the first interconnect after the step (c) and before the step (d).

10. The method of claim 9 , wherein

a main material of the cover layer is nickel, nickel alloy, cobalt, or cobalt alloy.

11. The method of claim 1 , further comprising the step of

(e1) exposing the surface of the protective film to plasma after the step (e).

12. The method of claim 11 , wherein

the plasma is generated in an atmosphere including a nitrogen compound.

13. The method of claim 1 , further comprising the step of

(e2) exposing the surface of the protective film to ultraviolet radiation after the step (e).

14. The method of claim 1 , further comprising the step of

(e3) forming a stopper film on the protective film after the step (e).

15. The method of claim 14 , wherein

the stopper film is an oxygen doped silicon carbide film or a silicon nitride film.

16. The method of claim 1 , wherein

the reaction layer is a silicon compound layer or a germanium compound layer.

17. The method of claim 1 , wherein

a main material of the first interconnect is aluminum, aluminum alloy, copper, copper alloy, silver, silver alloy, gold, or gold alloy.

18. A method of manufacturing a semiconductor device, the method comprising the steps of:

forming a first insulating film on a semiconductor substrate;

forming an interconnect groove in the first insulating film;

forming a first interconnect in the interconnect groove; and

forming a reaction layer in an upper part of the first interconnect, wherein

the reaction layer is formed under a condition where a supply rate controls a reaction.

19. The method of claim 18 , wherein

the reaction layer is a silicon compound layer or a germanium compound layer.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0870 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →