IP Library Granted Patent US 8,779,626
Granted Patent B2
US 8,779,626 · App. 13/274,654 · Granted Jul 15, 2014

Power management with over voltage protection

Inventors: Gregory A. Maher (Cape Elizabeth, ME); Myron J. Miske (Newfields, NH)
Assignee: Fairchild Semiconductor Corporation
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Quick Facts
Patent No.
US 8,779,626
App. No.
13/274,654
Granted
Jul 15, 2014
Kind
B2
Abstract

This document discusses, among other things, systems and methods to provide an internal supply rail with over voltage protection using a host power source, an external power source, and a switch configured to receive indications of host and external power source validity. In an example, the switch can be configured to provide the internal supply rail using the host power source when the indication of host power source validity indicates a valid host power source and the external power source when the indication of host power source validity indicates an invalid host power source and the indication of external power source validity indicates a valid external power source.

Claims (61)

1. A power management circuit, comprising:

a switch configured to receive a host power source, an external power source, an indication of host power source validity, and an indication of external power source validity;

wherein the switch is configured to provide an internal supply rail using (1) the host power source when the indication of host power source validity indicates a valid host power source, and (2) the external power source when the indication of host power source validity indicates an invalid host power source and the indication of external power source validity indicates a valid external power source; and

an over voltage protection circuit, including:

an over voltage detection circuit configured to detect an over voltage condition on the external power source; and

a clamp circuit configured to clamp the external power source when the over voltage detection circuit detects the over voltage condition on the external power source.

2. The power management circuit of claim 1 , including:

a host power source detection circuit configured to validate the host power source and to provide the indication of host power source validity; and

an external power source detection circuit configured to validate the external power source and to provide the indication of external power source validity;

wherein the host power source includes a battery, and wherein the external power source includes an external bus voltage.

3. The power management circuit of claim 2 , wherein the clamp circuit includes a clamp switch configured to selectively short the clamp circuit for an initial time period when the indication of external power source validity indicates a valid external power source.

4. The power management circuit of claim 2 , including a bandgap reference circuit configured to provide a bandgap voltage reference;

wherein the host power source detection circuit includes a comparator configured to validate the host power source using the value of the host power source and the bandgap voltage reference; and

wherein the external power source detection circuit includes a comparator configured to validate the external power source using the value of the external power source and the bandgap voltage reference.

5. The power management circuit of claim 1 , including a voltage regulator configured to provide a regulated external power source; and

wherein the switch is configured to provide the internal supply rail using the regulated external power source when the indication of host power source validity indicates an invalid host power source and the indication of external power source validity indicates a valid external power source.

6. The power management circuit of claim 1 , wherein the switch includes:

a first input configured to receive the host power source;

a second input configured to receive the external power source;

a first control input configured to receive the indication of the host power source validity;

a second control input configured to receive the indication of the external power source validity; and

an output configured to provide an internal supply rail.

7. The power management circuit of claim 1 , wherein the clamp circuit includes a clamp switch configured to selectively short the clamp circuit when the over voltage detection circuit does not detect the over voltage condition on the external power source.

8. The power management circuit of claim 7 , wherein the clamp switch includes a transistor;

wherein the clamp circuit includes a clamp control circuit including an oscillator, a counter, and a charge pump; and

wherein the clamp control circuit is configured to receive an indication of a detected over voltage condition and to control the clamp switch using the indication of over voltage detection circuit detects the over voltage condition on the external power source.

9. A power management method, comprising:

receiving indications of host and external power source validities;

providing an internal supply rail using a host power source when the indication of host power source validity indicates a valid host power source;

providing an internal supply rail using an external power source when the indication of host power source validity indicates an invalid host power source and the indication of external power source validity indicates a valid external power source;

detecting an over voltage condition on the external power source; and

clamping the external power source using a clamp circuit when the over voltage condition is detected on the external power source.

10. The method of claim 9 , including:

validating the host power source and providing the indication of host power source validity; and

validating the external power source and providing the indication of external power source validity.

11. The method of claim 10 , including selectively shorting the clamp circuit for an initial time period when the indication of external power source validity indicates a valid external power source.

12. The method of claim 10 , including:

providing a bandgap voltage reference;

validating the host power source using the value of the host power source and the bandgap voltage reference; and

validating the external power source using the value of the external power source and the bandgap voltage reference.

13. The method of claim 9 , including providing a regulated external power source; and

wherein the providing the internal supply rail includes using the regulated external power source when the indication of host power source validity indicates an invalid host power source and the indication of external power source validity indicates a valid external power source.

14. The method of claim 9 , including selectively shorting a clamp circuit when the over voltage detection circuit does not detect an over voltage condition on the external power source.

15. The method of claim 14 , including:

receiving an indication of a detected over voltage condition on the external power source; and

controlling the clamp circuit using the indication of over voltage detection detects the over voltage condition on the external power source.

16. A power management system, comprising:

an electronic device, including a host power source and a universal serial bus (USB) port, the USB port configured to receive an external power source;

a switch configured to receive the host power source, the external power source, an indication of host power source validity, and an indication of external power source validity;

wherein the switch is configured to provide an internal supply rail using (1) the host power source when the indication of host power source validity indicates a valid host power source, and (2) the external power source when the indication of host power source validity indicates an invalid host power source and the indication of external power source validity indicates a valid external power source;

an over voltage protection circuit, including:

an over voltage detection circuit configured to detect an over voltage condition on the external power source; and

a clamp circuit configured to clamp the external power source when the over voltage detection circuit detects the over voltage condition on the external power source.

17. The power management system of claim 16 , including:

a host power source detection circuit configured to validate the host power source and to provide the indication of host power source validity; and

an external power source detection circuit configured to validate the external power source and to provide the indication of external power source validity.

18. The power management system of claim 17 , wherein the clamp circuit includes a clamp switch configured to selectively short the clamp circuit for an initial time period when the indication of external power source validity indicates a valid external power source.

19. The power management system of claim 17 , including a bandgap reference circuit configured to provide a bandgap voltage reference;

wherein the host power source detection circuit includes a comparator configured to validate the host power source using the value of the host power source and the bandgap voltage reference; and

wherein the external power source detection circuit includes a comparator configured to validate the external power source using the value of the external power source and the bandgap voltage reference.

20. The power management circuit of claim 16 , wherein the clamp circuit includes a clamp switch configured to selectively short the clamp circuit when the over voltage detection circuit does not detect the over voltage condition on the external power source.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2012
From: MAHER, GREGORY A.; MISKE, MYRON J.
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 028914/0467 →
Continuity (2)
Provisional Application 61393795 · Oct 15, 2010
Related Publication 20120126625A1 · May 24, 2012