Systems and methods for a fast interconnect table
View Patent ↗In a multi-processor (e.g., multi-core) computer system, several processors can simultaneously access data without corruption thereof by: designating to each processor a portion of a hash table containing the data; by allowing each processor to access only those data elements belonging to the portion of the hash table designated to that processor; and by sending, via a network, other data elements to the processors that are designated the portions of the hash table to which the other data elements belong. The network avoids memory contention at each processor without requiring a memory-based lock. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.
1. A method of allowing a processing element access to data, the method comprising:
determining, at a first processing element, based on a first function, if a datum is to be processed by the first processing element;
if the datum is determined to be processed by the first processing element: (i) selecting a table location based on the datum and a second function, the selected table location being designated to the first processing element, and (ii) accessing the datum at the selected table location; and
if the datum is determined not to be processed by the first processing element, communicating the datum to a second processing element, using a network configured to avoid contention for memory designated to the second processing element if the second processing element and any other processing element simultaneously access any data in the memory designated to the second processing element.
2. The method of claim 1 , wherein the selected table location corresponds to memory designated to the first processing element.
3. The method of claim 2 , wherein the memory designated to the first processing element comprises:
a cache memory allocated to the first processing element; and
a main memory.
4. The method of claim 2 , wherein the second function causes: (i) the selected table location to belong to a first bucket of memory locations within the memory designated to the first processing element, and (ii) a size of the first bucket to be less than or equal to a cache-line size of the memory.
5. The method of claim 1 , wherein the second processing element is designated to process the datum.
6. The method of claim 1 , wherein the accessing comprises at least one of reading the datum or storing the datum.
7. The method of claim 1 , wherein the communicating the datum comprises inserting the datum in a queue of data elements at the second processing element, each element in the queue accessing the memory designated to the second processing element in a sequence, thereby avoiding contention for the memory.
8. The method of claim 1 , wherein the selected table location belongs to a first bucket of memory locations within a memory designated to the first processing element, the method further comprising growing the first bucket of memory locations.
9. The method of claim 8 , wherein growing comprises linking to the first bucket of memory locations a memory buffer having a size equal to the size of the first bucket.
10. The method of claim 8 , wherein growing comprises:
forming a second bucket of memory locations associated with the first bucket; and
selecting a function to distribute data stored in the first bucket between the first and second buckets.
11. The method of claim 1 , wherein the first and the second processing elements are located on a single chip.
12. A computing apparatus for accessing data, the computing apparatus comprising:
a processor; and
a memory coupled to the processor, wherein the processor is configured:
to determine, based on a first function, if a datum is to be processed by the processor;
if the datum is determined to be processed by the processor: to (i) select a table location based on the datum and a second function, the selected table location being designated to the processor, and (ii) access the datum at the selected table location; and
if the datum is determined not to be processed by the processor, to communicate the datum to another processor, using a network configured to avoid contention for memory designated to the second processor if the second processor and any other processor simultaneously access any data in the memory designated to the second processor.
13. The computing apparatus of claim 12 , wherein the selected table location corresponds to the memory coupled to the processor.
14. The computing apparatus of claim 12 , wherein the memory coupled to the processor comprises:
a cache memory allocated to the processor; and
a main memory.
15. The computing apparatus of claim 12 , wherein the second function causes: (i) the selected table location to belong to a first bucket of memory locations within the memory coupled to the processor, and (ii) a size of the first bucket to be less than or equal to a cache-line size of the memory.
16. The computing apparatus of claim 12 , wherein the access comprises at least one of reading the datum or storing the datum.
17. The computing apparatus of claim 12 , further comprising a network interface in communication with the network and the processor, wherein the network interface is configured to:
create a queue of data elements;
receive a data element via the network; and
insert the received data element in the queue, such that each data element in the queue accesses the memory coupled to the processor in a sequence, thereby avoiding contention for the memory.
18. The computing apparatus of claim 12 , wherein the selected table location belongs to a first bucket of memory locations within the memory coupled to the processor, and the processor is further configured to grow the first bucket of memory locations.
19. The computing apparatus of claim 18 , wherein the processor is further configured to link to the first bucket of memory locations a memory buffer having a size equal to the size of the first bucket, thereby growing the first bucket.
20. The computing apparatus of claim 18 , wherein the processor is further configured to:
form a second bucket of memory locations associated with the first bucket; and
select and execute a function to distribute data stored in the first bucket between the first and second buckets, thereby growing the first bucket.
21. The computing apparatus of claim 12 , wherein the processor and the other processor are located on a single chip.
22. An article of manufacture, comprising a non-transitory machine-readable medium storing instructions that, when executed by a first processing element, configure the first processing element to:
determine, based on a first function, if a datum is to be processed by the first processing element;
if the datum is determined to be processed by the first processing element: (i) to select a table location based on the datum and a second function, the selected table location being designated to the first processing element, and (ii) to access the datum at the selected table location; and
if the datum is determined not to be processed by the first processing element, to communicate the datum to a second processing element, using a network configured to avoid contention for memory designated to the second processing element if the second processing element and any other processing element simultaneously access any data in the memory designated to the second processing element.
23. The article of claim 22 , wherein the selected table location corresponds to memory designated to the first processing element.
24. The article of claim 23 , wherein the memory designated to the first processing element comprises:
a cache memory allocated to the first processing element; and
a main memory.
25. The article of claim 23 , wherein the second function causes: (i) the selected table location to belong to a first bucket of memory locations within the memory designated to the first processing element, and (ii) a size of the first bucket to be less than or equal to a cache-line size of the memory.
26. The article of claim 22 , wherein the second processing element is designated to process the datum.
27. The article of claim 22 , wherein the access comprises at least one of reading the datum or storing the datum.
28. The article of claim 22 , wherein the instructions configure the second processing element to insert the datum in a queue of data elements at the second processing element, each element in the queue accessing the memory designated to the second processing element in a sequence, thereby avoiding contention for the memory.
29. The article of claim 22 , wherein the selected table location belongs to a first bucket of memory locations within a memory designated to the first processing element, and the instruction further configure the first processing element to grow the first bucket of memory locations.
30. The article of claim 29 , wherein the instruction further configure the first processing element to link to the first bucket of memory locations a memory buffer having a size equal to the size of the first bucket, thereby growing the first bucket.
31. The article of claim 29 , wherein the instruction further configure the first processing element to:
form a second bucket of memory locations associated with the first bucket; and
select a function to distribute data stored in the first bucket between the first and second buckets, thereby growing the first bucket.
32. The article of claim 22 , wherein the first and the second processing elements are located on a single chip.