SUBSTRATE FOR A MICROELECTRONIC PACKAGE AND METHOD OF FABRICATING THEREOF

1 . A microelectronic substrate having a plurality of traces for electrical interconnection with external contacts of a semiconductor chip mountable thereto, comprising:

a plurality of etched metal first contact pins, each first pin having a base and a tip;

a plurality of first conductive traces adapted for electrical connection with the external semiconductor chip, at least some of the first traces being coupled to the bases of the first pins so that the first pins project downwardly from the first traces; and

a molded dielectric layer disposed in regions around the first pins and having an exposed bottom surface coplanar with the tips of the first pins, a top surface remote from the bottom surface, wherein the first traces extend along the top surface of the molded dielectric layer, and at least some of the tips of the first pins are exposed at the bottom surface of the dielectric layer,

wherein the top surface of said dielectric layer is coplanar with the bases of the first pins, said first traces extending over the top surface of said dielectric layer,

the first traces include an electrically conductive principal metal and a conductive barrier layer formed of Ni disposed between the principal metal and the bases of the first pins, and the first pins form at least one grid-like pattern having a pitch in range from 100 to 10000 μm,

wherein widths of the first traces are equal to or smaller than widths of the bases of the first pins coupled to the first traces,

the first traces and the first pins predominantly include Cu, the dielectric layer predominantly includes epoxy, the molded dielectric layer is formed by introducing a flowable composition between the first pins and curing the same, and the first pins are formed by etching a metal plate.