Control circuit for an internal voltage generation circuit
View Patent ↗Sharp fluctuations of an internal voltage when an internal voltage generating circuit is activated or inactivated are prevented. The internal voltage generating circuit to supply the internal voltage generated from an external voltage to an internal power supply line, a control circuit to control an operation of the internal voltage generating circuit, and a voltage detection circuit to detect a level of a first voltage are included. When, for example, the internal voltage generating circuit is activated, the control circuit stepwise increases supply ability of the internal voltage at a first speed and when the internal voltage generating circuit is inactivated, the control circuit stepwise reduces the supply ability of the internal voltage at a second speed that is different from the first speed. Accordingly, wild fluctuations of the internal voltage when the internal voltage generating circuit is activated/inactivated can optimally be prevented for each case.
1. A semiconductor device comprising:
an oscillation circuit configured to produce an oscillator signal;
an internal voltage generating circuit including first and second charge pump circuits each including an output node coupled to a common node;
a first control circuit configured to receive the oscillator signal and produce a first control signal and a second control signal;
a second control circuit configured to receive the oscillator signal and the first control signal to operate the first charge pump circuit; and
a third control circuit configured to receive the oscillator signal and the second control signal to operate the second charge pump circuit,
wherein the first control signal includes a first activation signal to activate the first charge pump circuit and a first inactivation signal to inactivate the first charge pump circuit,
wherein the second control signal includes a second activation signal to activate the second charge pump circuit and a second inactivation signal to inactivate the second charge pump circuit, and
wherein the first control circuit is configured to produce the first and second activation signals independently to each other, and produce the first and second inactivation signals independently to each other.
2. The semiconductor device as claimed in claim 1 ,
wherein timings of the first and second activation signals are different from timings of the first and second inactivation signals.
3. The semiconductor device as claimed in claim 2 ,
wherein the timings of the first and second activation signals are changed based on a voltage inputted from an outside of the semiconductor device.
4. The semiconductor device as claimed in claim 3 ,
wherein the timings of the first and second inactivation signals are changed based on the voltage inputted from the outside of the semiconductor device.
5. A semiconductor device comprising:
an oscillation circuit configured to produce an oscillator signal;
an internal voltage generating circuit including first and second charge pump circuits each including an output node coupled to a common node;
a first control circuit configured to receive the oscillator signal and produce a first control signal and a second control signal;
a second control circuit configured to receive the oscillator signal and the first control signal to operate the first charge pump circuit;
a third control circuit configured to receive the oscillator signal and the second control signal to operate the second charge pump circuit; and
a first voltage detection circuit configured to detect an external voltage and produce a third control signal which is applied to the first control circuit.
6. The semiconductor device as claimed in claim 5 , the semiconductor device further comprising:
a second voltage detection circuit configured to detect an internal voltage on the common node and produce a fourth control signal which is applied to the oscillation circuit.
7. A semiconductor device comprising:
an oscillation circuit configured to produce an oscillator signal;
an internal voltage generating circuit including first and second charge pump circuits each including an output node coupled to a common node;
a first control circuit configured to receive the oscillator signal and produce a first control signal and a second control signal;
a second control circuit configured to receive the oscillator signal and the first control signal to operate the first charge pump circuit; and
a third control circuit configured to receive the oscillator signal and the second control signal to operate the second charge pump circuit,
wherein the first control circuit further produces a fourth control signal and a fifth control signal applied to the first and second charge pump circuits, respectively, to control the first and second charge pumps to change an ability supplying a power source voltage to the common node by the respective first and second charge pump circuits.
8. The semiconductor device as claimed in claim 7 ,
wherein changing the ability is based on a voltage level of a voltage supplied from an outside of the semiconductor device.
9. A semiconductor device comprising:
an oscillation circuit configured to produce an oscillator signal;
an internal voltage generating circuit including first and second charge pump circuits each including an output node coupled to a common node;
a first control circuit configured to receive the oscillator signal and produce a first control signal and a second control signal;
a second control circuit configured to receive the oscillator signal and the first control signal to operate the first charge pump circuit; and
a third control circuit configured to receive the oscillator signal and the second control signal to operate the second charge pump circuit,
wherein the first control circuit comprises:
a counter circuit producing a plurality of selection signals; and
a selection circuit receiving the plurality of selection signals to produce the first and second control signals.
10. The semiconductor device as claimed in claim 9 , wherein the counter circuit comprises:
a start counter circuit producing a first group of the plurality of selection signals, the selection signals of the first group being different in timing to one another; and
an exit counter circuit producing a second group of the plurality of selection signals, the selection signals of the second group being different in timing to one another.
11. The semiconductor device as claimed in claim 10 , wherein the selection circuit comprises:
a first group of selectors each receiving corresponding ones of the first group of the selection signals to selectively output one of the ones of the first group of the selection signals; and
a second group of selectors each receiving corresponding ones of the second group of the selection signals to selectively output one of the ones of the second group of the selection signals.
12. The semiconductor device as claimed in claim 9 , wherein the counter circuit is reset when a count value thereof exceeds a predetermined value.
13. The semiconductor device as claimed in claim 12 , wherein the first control circuit maintains an active state of the oscillator until the counter circuit is reset.