SYSTEMS AND METHODS FOR SUPPRESSING UNDESIRABLE LIMIT CYCLES IN SWITCHING REGULATORS
This disclosure involves methods and systems for suppressing undesired limit cycles in switching regulators by determining when a limit cycle causes the inductor to charge for a time greater than the clock period and destabilizing such cycles.
1 . A method for controlling a switching regulator having an inductor coupled to a load and a clock having regular timing cycles T, comprising the steps of:
a) determining whether an undesirable limit cycle exists;
b) sending a control signal to switch the inductor to a charge state at a first time during each timing cycle;
c) sensing a current across the inductor;
d) when an undesirable limit cycle does not exist, sending a control signal within one timing cycle from the first time to switch the inductor to a discharge state if the current across the inductor reaches a threshold value; and
e) when an undesirable limit cycle does exist, sending a control signal after at least one timing cycle from the first time to switch the inductor to a discharge state.
2 . The method of claim 1 , wherein the step of determining whether an undesirable limit cycle exists comprises determining whether the inductor is kept in a charge state for greater than one time cycle T.
3 . The method of claim 2 , wherein the step of determining whether an undesirable limit cycle exists comprises determining whether the inductor is already switched to a charge state at the first time.
4 . The method of claim 3 , wherein the step of determining whether an undesirable limit cycle exists further comprises determining a period NT of the undesirable limit cycle.
5 . The method of claim 4 , wherein the step of determining the period NT of the undesirable limit cycle comprises counting a number of consecutive timing cycles for which the inductor is already switched to a charge state at the first time of each timing cycle.
6 . The method of claim 4 , wherein the step of sending a control signal after at least one timing cycle from the first time to switch the inductor to a discharge state comprises disabling the sending of the control signal until N−1 timing cycles have occurred.
7 . The method of claim 1 , wherein the step of determining whether an undesirable limit cycle exists includes determining when the ratio of a rate during the charge state to a rate during the discharge state is greater than one.
8 . The method of claim 1 , wherein the step of determining whether an undesirable limit cycle exists includes determining whether a time the inductor is in the discharge state is greater than one time cycle.
9 . A switching regulator comprising an inductor coupled to a load, a clock having regular timing cycles T, a switching system for alternately connecting the inductor to an input voltage source and a low impedance source and a controller, wherein the controller is configured to:
a) determine whether an undesirable limit cycle exists;
b) send a control signal to the switching system to connect the inductor to the input voltage source and place the inductor in a charge state at a first time during each timing cycle;
c) sense a current across the inductor;
d) when an undesirable limit cycle does not exist, send a control signal within one timing cycle from the first time to the switching system to disconnect the inductor from the input voltage and place the inductor in a discharge state if the current across the inductor reaches a threshold value; and
e) when an undesirable limit cycle does exist, send a control signal after at least one timing cycle from the first time to the switching system to disconnect the inductor from the input voltage and place the inductor in a discharge state.
10 . The regulator of claim 9 , wherein the controller is configured to determine whether an undesirable limit cycle exists by determining whether the inductor is kept in a charge state for greater than one time cycle T.
11 . The regulator of claim 10 , wherein the controller is configured to determine whether an undesirable limit cycle exists comprises determining whether the inductor is already switched to a charge state at the first time.
12 . The regulator of claim 11 , wherein the controller is configured to determine a period NT of the undesirable limit cycle.
13 . The regulator of claim 12 , wherein the controller is configured to determine the period NT of the undesirable limit cycle by counting a number of consecutive timing cycles for which the inductor is already switched to a charge state at the first time of each timing cycle.
14 . The regulator of claim 12 , wherein the controller is configured to disable the sending of the control signal until N−1 timing cycles have occurred when an undesirable limit cycle exists.
15 . The regulator of claim 9 , wherein the controller is configured to determine when the ratio of a rate during the charge state to a rate during the discharge state is greater than one.
16 . The regulator of claim 9 , wherein the controller is configured to determine whether a time the inductor is in the discharge state is greater than one time cycle.