Split varactor array with improved matching and varactor switching scheme

1. A digital controlled oscillator, comprising:

an oscillator circuit configured to receive a control word and configured to generate an oscillator clock signal at a frequency selected by the control word;

a varactor array having a first array of varactor cells having incremental capacitance values starting from a base capacitance value, wherein the incremental capacitance values are sequential integer multiples of the base capacitance value, wherein each of the varactor cells of the first array include an identical number of capacitors, each capacitor having a capacitance of the base capacitance value and at least a portion of the varactor cells configured to have one or more of its capacitors unconnected as dummy capacitors; and

a control circuit coupled to the oscillator circuit configured to control the varactor array according to the control word.

2. The oscillator of claim 1 , wherein the varactor array further comprises a second array of equal capacitance values.

3. The oscillator of claim 1 , further comprising a coupling network to couple an output of the varactor array to an output of the oscillator circuit.

4. The oscillator of claim 1 , wherein the control word is time varying digital information.

5. The oscillator of claim 1 , wherein the oscillator clock signal is configured to have a specified step size.

6. The oscillator of claim 5 , wherein a lowest bit of the control word corresponds to the specified step size.

7. The oscillator of claim 1 , wherein the first array comprises a number of cells ranging from one to a selected number, and wherein the size of each cell ranges from unity to unity multiplied by the selected number.

8. The oscillator of claim 7 , wherein the varactor array further comprises a second array having a plurality of varactor cells, wherein the size of each of the plurality of varactor cells is the sum of the selected number and one multiplied by unity.

9. The oscillator of claim 8 , wherein the second array is configured with a top bank and a bottom bank.

10. The oscillator of claim 8 , wherein the varactor array further comprises a third array.

11. The oscillator of claim 10 , wherein the third array has a varactor cell having a size less than unity.

12. The oscillator of claim 10 , wherein the third array has varactor cell sizes greater than the selected number multiplied by unity.

13. A phase locked loop circuit comprising:

a digital controlled oscillator configured to receive a phase component and a control word and to generate an oscillator clock signal at a frequency selected by the control word, the digital controlled oscillator comprising;

a varactor array having a first array of varactor cells with incremental capacitance values, wherein only one of the varactor cells can be on at any time and each cell includes a plurality of capacitors, wherein each of the varactor cells of the varactor array include an identical number of capacitors, each capacitor having a capacitance of the base capacitance value and at least a portion of the varactor cells configured to have one or more of its capacitors unconnected as dummy capacitors; and

a control circuit coupled to the oscillator circuit configured to control the varactor array according to the control word; and

a phase divider configured to divide the oscillator clock into a phase modulated signal.

14. The circuit of claim 13 wherein the control word of the digitally controlled oscillator is provided for modulation.

15. The circuit of claim 13 wherein each bit of the control word corresponds to a frequency step size.

16. The circuit of claim 15 where the frequency step size of the digitally controlled oscillator is a step size variation from a prior control word.

17. The circuit of claim 13 where the digital controlled oscillator further comprises a coarse tuning component coupled to the controller and having a capacitor arrangement.

18. The circuit of claim 13 , wherein the varactor array further comprises a second array of equal capacitance values.

19. A method of generating an oscillator clock signal, the method comprising:

receiving a signal;

receiving a control word designating a selected frequency;

providing a varactor array having a first array of varactor cells of incremental capacitance values starting from a base capacitance value and a second array of varactor cells of equal capacitance values, wherein the incremental capacitance values are sequential integer multiples of the base capacitance value, and wherein each of the varactor cells of the first array include an identical number of capacitors, each capacitor having a capacitance of the base capacitance value and at least a portion of the varactor cells of the first array configured to have one or more of its capacitors unconnected as dummy capacitors;

turning on one or more cells of the varactor array to yield a capacitance value according to the selected frequency; and

generating an oscillator clock signal from the received signal at the selected frequency using the capacitance value.

20. The method of claim 19 , further comprising receiving a second control word designating a step size decrease in frequency and turning off a first cell of the varactor array and turning on a second cell of the varactor array to yield a second capacitance value according to the step size decrease in frequency.

21. The oscillator of claim 1 , wherein at least a portion of the varactor cells include dummy capacitors and active capacitors, wherein the dummy capacitors are present within the cell and are not turned ON when the cells are turned ON.