Clock and data recovery for NFC transceivers
Exemplary embodiments are directed to data and clock recovery in NFC transceivers. A transceiver may include a phase-locked loop configured to recover a clock from a received input signal in a first mode and enable for oversampling of an output signal in a second, different mode.
1. A circuit comprising a phase-locked loop configured to recover a clock from a received input signal in a first mode and the phase-locked loop further configured for oversampling of an output signal in a second, different mode, the phase-locked further configured to detect an amplitude-shift keying mode wherein the input signal undergoes 100% amplitude-shift keying of lacking a transition of the input signal over a plurality of samples.
2. The circuit of claim 1 , the phase-locked loop comprising a first voltage controlled oscillator for use in the first mode and a second voltage controlled oscillator for use in the second mode.
3. The circuit of claim 1 , the phase-locked loop comprising a phase-frequency detector including an amplitude-shift keying detection circuit configured to detect the amplitude-shift keying mode.
4. The circuit of claim 3 , the amplitude-shift keying detection circuit comprising a plurality of flip-flop circuits.
5. The circuit of claim 1 , the phase-locked loop comprising a plurality of multiplexers for selecting one of a first path and a second path.
6. The circuit of claim 5 , the first path configured for a first frequency and a first power level and the second path configured for a second frequency greater than the first frequency and a second power level greater than the first power level.
7. The circuit of claim 1 , the phase-locked loop comprising:
a first circuit path including a first voltage controlled oscillator, the first circuit path for oversampling of the output signal; and
a second circuit path including a first voltage controlled oscillator having a frequency lower than a frequency of the first voltage controlled oscillator, the second circuit path for recovering the clock from the received input signal.
8. A circuit, comprising:
a frequency-phase detector; and
an amplitude-shift keying detection circuit coupled to the frequency-phase detector and configured to detect an amplitude-shift keying mode wherein a signal undergoes 100% amplitude-shift keying of lacking a transition of the signal over a plurality of samples.
9. The circuit of claim 8 , the amplitude-shift keying detection circuit comprising a plurality of flip-flop circuits configured to detect 100% amplitude-shift keying.
10. The circuit of claim 9 , each flip-flop circuit of the plurality of flip-flops configured to sample an input signal at an edge of an associated voltage controlled oscillator signal.
11. The circuit of claim 9 , the amplitude-shift keying detection circuit further comprising a XOR gate coupled to an output of each flip-flop of the plurality of flip-flops.
12. The circuit of claim 8 , the amplitude-shift keying detection circuit configured to convey a signal to the frequency-phase detector to reset the frequency-phsae detector upon detection of the amplitude-shift keying mode.
13. The circuit of claim 8 , an output of the amplitude-shift keying detection circuit coupled to an NAND gate of the frequency-phase detector.
14. A method, comprising:
recovering a clock from a received input signal with a phase-locked loop in a first near-field communication (NFC) mode;
detecting an amplitude-shift keying mode wherein the input signal undergoes 100% amplitude-shift keying of lacking a transition of the input signal over a plurality of samples; and
oversampling of an output signal with the phase-locked loop in a second, different NFC mode, the recovering comprising utilizing a first circuit path of the phase-locked loop and the oversampling comprising utilizing a second, different circuit path of the phase-locked loop.
15. The method of claim 14 , the recovering comprising recovering the clock from the received input signal in a tag mode.
16. The method of claim 14 , the oversampling comprising oversampling the output signal in an initiator mode.
17. A method, comprising:
receiving an input signal at a phase-frequency detector in a tag mode; and
detecting an amplitude-shift keying mode wherein the input signal undergoes 100 % amplitude-shift keying of lacking a transition of the input signal over a plurality of samples while receiving the input signal in the tag mode.
18. The method of claim 17 , further comprising resetting the phase-frequency detector upon detecting the amplitude-shift keying mode.
19. The method of claim 17 , the detecting comprising detecting a consecutive number of zeros in the input signal.
20. The method of claim 17 , the detecting comprising sampling the input signal with a plurality of flip-flop circuits.
21. The method of claim 17 , the sampling comprising sampling the input signal at each of a rising edge and a falling edge of an output of an associated voltage controlled oscillator.
22. A device, comprising:
means for recovering a clock from a received input signal in a first NFC mode, the means for recovering utilizing a first circuit path of a phase-locked loop means;
means for detecting an amplitude-shift keying mode wherein the input signal undergoes 100% amplitude-shift keying of lacking a transition of the input signal over a plurality of samples; and
means for oversampling of an output signal in a second, different near-field communication (NFC) mode, the means for oversampling utilizing a second, different circuit path in a phase-locked loop means.
23. A device, comprising:
means for receiving an input signal in a tag mode; and
means for detecting an amplitude-shift keying mode wherein the input signal undergoes 100% amplitude-shift keying of lacking a transition of the input signal over a plurality of samples while receiving the input signal in the tag mode.