Dual speed readout integrated circuit for high spatial and temporal resolution applications

1. A dual speed readout integrated circuit comprising:

a native pixel array with associated high resolution integration circuits for each pixel wherein each native pixel in the native pixel array comprises:

a detector;

a first integration capacitor connected to the detector and a second integration capacitor connected to the detector; and,

a sample and hold capacitor selectably connectable to the first integration capacitor;

a superpixel array created from the entire native pixel array by combination of native pixels in superpixels for charge sharing integration in reduced resolution integration circuits simultaneously with the integration of the high resolution integration circuits wherein each superpixel in the superpixel array includes a second sample and hold capacitor selectively connectable to the second integration capacitor in each native pixel combined for the superpixel;

switching control for readout of the high resolution integration circuits at a first frame rate; and

switching control for readout of the reduced resolution integration circuits at a second frame rate.

2. The dual speed readout integrated circuit as defined in claim 1 wherein connection of the sample and hold capacitor to the first integration capacitor is accomplished by a first switch operating one time per frame and connection of the second sample and hold capacitor to the second integration capacitor in each native pixel is accomplished by a second switch operating 16 times per frame.

3. A method for dual speed readout in an infrared sensor readout integrated circuit comprising:

resetting a first and a second integration capacitor in each unit cell of an array of unit cells;

beginning integration;

isolating the second integration capacitor;

resetting a first sample and hold capacitor;

resetting a second sample and hold capacitor associated with a superpixel of a plurality of unit cells in the unit cell array;

connecting the second sample and hold capacitor to the second integration capacitor in each of the unit cells in the superpixel and reading the second sample and hold capacitor at a first sample rate; and,

connecting the first sample and hold capacitor to the first integration capacitor and reading the first sample and hold capacitor at a second sample rate.

4. The method of claim 3 wherein the superpixel comprises at least a 4×4 matrix of unit cells.

5. The method of claim 4 wherein the array of unit cells comprises at least 1280×1024 unit cells.

6. The method of claim 3 wherein the second sample rate comprises once per frame.

7. The method of claim 6 wherein the first sample rate comprises 16 times per frame.