Semiconductor system, relay apparatus, and chip circuit
View Patent ↗Highly efficient and low latency network transmission in consideration of a difference in the traffic characteristic and a memory access load which changes moment by moment is realized. A relay device transmits data on a networked communication bus between a bus master and a memory. The relay device includes a delay time processor for obtaining information on processing delay time in other relay devices located on a plurality of transmission routes on which the data is transmitted; and a low latency route selector for selecting a memory and one of transmission routes to the memory, among the plurality of transmission routes, based on obtained information on the processing delay time regarding the plurality of transmission routes.
1. A semiconductor system, comprising:
at least one first node;
a plurality of second nodes; and
a relay device for relaying data transmitted from the at least one first node via a networked communication bus and transmitting the data to one of the plurality of second nodes;
wherein:
the relay device is connected to the at least one first node;
the relay device includes a low latency route selector for selecting a set of a second node and a transmission route from combinations of each of the plurality of second nodes and each of a plurality of transmission routes, based on information on a load value of each of the second nodes and information on a load value of each of the transmission routes; and
the relay device uses the transmission route selected by the low latency route selector to relay the data toward the selected second node,
wherein the low latency route selector uses at least one of a buffer amount, latency of a packet, throughput and jitter of a relay device immediately before each of the second nodes, as the load value of each of the second nodes.
2. The semiconductor system of claim 1 , wherein the low latency route selector uses at least one of the number of relay stages, a data length, a bus width and a bus band as the load value of each of the transmission routes.
3. The semiconductor system of claim 1 , wherein the low latency route selector selects the second node and the transmission route for which a sum of an evaluation value of a forward path between the at least one first node and the second node and an evaluation value of a return path between the at least one first node and the second node is smallest.
4. The semiconductor system of claim 1 , wherein the low latency route selector assembles traffics having a drastic change of peak or generated in a single, independent manner to one, same transmission route or second node with priority.
5. The semiconductor system of claim 1 , wherein the plurality of second nodes include at least one of a memory, a processor, and a digital signal processor.
6. The semiconductor system of claim 1 , wherein the plurality of second nodes include a relay device for connecting a plurality of networks.