Thin film transistor array panel and manufacturing method thereof
View Patent ↗A thin film transistor and a manufacturing method thereof are provided. In the manufacturing method of the thin film transistor a semiconductive active layer and a semiconductor passivation layer are sequentially formed such that the semiconductor passivation layer protectively covers the semiconductive active layer. Then the stacked combination of the semiconductive active layer and semiconductor passivation layer are patterned by using a same patterning mask so that formed islands of the semiconductive active layer continue to be protectively covered by formed islands of the semiconductor passivation layer. In one embodiment, the semiconductive active layer is formed of a semiconductive oxide.
1. A method for manufacturing a thin film transistor array panel, comprising:
forming a gate electrode on a substrate;
forming a gate insulating layer on the gate electrode;
depositing a semiconductive active layer on the gate insulating layer;
depositing an insulating layer on the semiconductive active layer;
patterning the semiconductive active layer and the insulating layer by using a same one pattern-defining mask to thereby form a corresponding patterned semiconductive active layer and a preliminarily patterned semiconductor passivation layer;
patterning the preliminary semiconductor passivation layer to form first and second openings defined through a corresponding patterned semiconductor passivation layer; and
forming a source electrode and a drain electrode on the patterned semiconductor passivation layer.
2. The method of claim 1 , wherein
the semiconductive active layer includes a semiconductive oxide material.
3. The method of claim 2 , wherein
the deposition of the semiconductive active layer and the deposition of the insulating layer are sequentially executed in a same sealed deposition apparatus.
4. The method of claim 3 , wherein
the deposition of the insulating layer includes use of a sputtering method.
5. The method of claim 3 , wherein
the deposition of the semiconductor and the deposition of the insulating layer are executed while the sealed deposition apparatus is in a vacuum state.
6. The method of claim 1 , wherein
the patterning of the semiconductive active layer and the insulating layer by using a same one pattern-defining mask includes
forming a photosensitive film pattern by using the one mask,
dry-etching the insulating layer by using the photosensitive film pattern, and
wet-etching the semiconductive active layer by using the photosensitive film pattern.
7. The method of claim 6 , wherein
a thickness of the semiconductive active layer is in the range of 250 Å to 1000 Å.
8. The method of claim 7 , wherein
the semiconductor passivation layer is formed of SiOx.
9. The method of claim 1 , further comprising forming a covering passivation layer on the source electrode and the drain electrode,
wherein the covering passivation layer contacts the semiconductive active layer through the first and second openings.