IP Library Granted Patent US 8,711,509
Granted Patent B2
US 8,711,509 · App. 13/285,472 · Granted Apr 29, 2014

Disk-based storage device having read channel memory that is selectively accessible to disk controller

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Quick Facts
Patent No.
US 8,711,509
App. No.
13/285,472
Granted
Apr 29, 2014
Kind
B2
Abstract

A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk. The control circuitry comprises a disk controller and read channel circuitry, with the read channel circuitry comprising a read channel memory. The control circuitry is further configured to selectively permit the disk controller to access the read channel memory. For example, the disk controller may be permitted to access the read channel memory only when the read channel circuitry is not performing a read operation.

Claims (44)

1. An apparatus comprising:

a read/write head configured to read data from and write data to a storage disk; and

control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk;

wherein the control circuitry comprises:

a disk controller; and

read channel circuitry comprising a read channel memory;

the control circuitry being configured to selectively permit the disk controller to access the read channel memory, wherein the disk controller is permitted to access the read channel memory when the read channel circuitry is not performing a read operation.

2. The apparatus of claim 1 wherein disk controller has at least one associated memory comprising at least one of an internal memory of the disk controller and an external memory of the control circuitry.

3. The apparatus of claim 1 wherein at least the disk controller and the read channel circuitry are collectively implemented in the form of a system-on-chip integrated circuit.

4. The apparatus of claim 1 wherein read channel circuitry comprises a high speed port through which the disk controller is selectively permitted to access the read channel memory.

5. The apparatus of claim 1 wherein the disk controller is permitted to access the read channel memory only when the read channel circuitry is not performing the read operation.

6. The apparatus of claim 1 wherein the control circuitry is configured to determine if the read channel circuitry is performing the read operation and to permit the disk controller to access the read channel memory only if the read channel circuitry is not performing the read operation.

7. The apparatus of claim 1 wherein the control circuitry is configured to determine if a memory transfer involving the disk controller is required, and if the memory transfer involving the disk controller is required, to further determine if the read channel circuitry is performing the read operation, wherein if the read channel circuitry is performing the read operation, the memory transfer is executed without utilizing the read channel memory, and if the read channel circuitry is not performing the read operation, the memory transfer is executed at least in part utilizing the read channel memory.

8. The apparatus of claim 7 wherein if the read channel circuitry is performing the read operation, the memory transfer is executed utilizing at least one of an internal memory of the disk controller and an external memory of the control circuitry comprising the read channel memory and the disk controller.

9. The apparatus of claim 1 further comprising a processor and a memory coupled to the processor, the processor being configured to execute software code stored in the memory, wherein the software code when executed causes the control circuitry to selectively control access of the disk controller to the read channel memory.

10. The apparatus of claim 1 wherein the disk controller is permitted to access the read channel memory for memory transfers including transferring data to or from at least one of an external memory, a processor and a host computer, and not including reading data from the storage disk.

11. A storage device comprising the apparatus of claim 1 and its associated storage disk.

12. The storage device of claim 11 wherein the storage device comprises a hard disk drive.

13. A virtual storage system comprising the apparatus of claim 1 .

14. A method comprising the steps of:

configuring a storage device to include read channel circuitry comprising a read channel memory; and

selectively permitting a disk controller of the storage device to access the read channel memory, wherein the step of selectively permitting the disk controller to access the read channel memory further comprises permitting the disk controller to access the read channel memory if the read channel circuitry is not performing a read operation.

15. The method of claim 14 wherein the step of selectively permitting the disk controller to access the read channel memory further comprises the step of:

determining if the read channel circuitry is performing the read operation; and

permitting the disk controller to access the read channel memory only if the read channel circuitry is not performing the read operation.

16. The method of claim 14 wherein the step of selectively permitting the disk controller to access the read channel memory further comprises the steps of:

determining if a memory access involving the disk controller is required;

if the memory access involving the disk controller is required, determining if the read channel circuitry is performing the read operation;

if the read channel circuitry is performing the read operation, executing the memory transfer without utilizing the read channel memory; and

if the read channel circuitry is not performing the read operation, executing the memory transfer at least in part utilizing the read channel memory.

17. The method of claim 16 wherein if the read channel circuitry is performing the read operation, the memory transfer is executed utilizing at least one of an internal memory of the disk controller and an external memory of control circuitry comprising the read channel memory and the disk controller.

18. A non-transitory computer-readable storage medium having embodied therein executable code for performing the steps of the method of claim 14 .

19. A processing system comprising:

a processing device; and

a storage device coupled to the processing device and comprising at least one storage disk;

wherein the storage device further comprises:

a read/write head configured to read data from and write data to the storage disk; and

control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk;

wherein the control circuitry comprises:

a disk controller; and

read channel circuitry comprising a read channel memory;

the control circuitry being configured to selectively permit the disk controller to access the read channel memory, wherein the disk controller is permitted to access the read channel memory when the read channel circuitry is not performing a read operation.

20. The system of claim 19 wherein the processing device comprises a computer that incorporates the storage device.

21. The system of claim 19 wherein the system comprises a virtual storage system that includes said storage device and one or more additional storage devices.

Assignments (9)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →