Direct DC coupled push-pull BJT driver for power amplifier with built-in gain and bias current signal dependent expansion
View Patent ↗A power amplifier having a driver stage and an output stage is configured to provide an amplified RF input signal. The driver stage of the power amplifier consists of one or more driver circuits consisting of a network of transistors, current sources, capacitive elements and resistive elements. An RF input signal is fed into the driver stage which is configured to provide a dynamic DC bias and an RF signal gain to a base terminal of a Bipolar Junction Transistor (BJT) power device present in the output stage. The output stage includes of a network of transistors, capacitive and resistive elements and when driven by the DC bias and the RF signal from the driver stage produces an amplified RF input signal at an output side of the output stage.
1. A driver circuit configured to provide dynamic DC bias and RF signal gain to a base terminal of a Bipolar Junction Transistor (BJT) power device in a power amplifier, the driver circuit comprising:
a first transistor with a first current flowing from a first terminal of the first transistor to a second terminal of the first transistor;
a second transistor with a second current flowing from a first terminal of the second transistor to a second terminal of the second transistor, wherein the first transistor and the second transistor are in a push-pull configuration;
a first current source connected to a first terminal of a first current mirror, wherein the first current source controls the first current; and
a second current source connected to a first terminal of a second current mirror, wherein the second current source controls the second current, the dynamic DC bias and the RF signal gain corresponding to a difference between the first current and the second current, wherein changing the ratio of the width of the first transistor to the width of the second transistor provides the dynamic DC bias and the RF signal gain to the base terminal of the Bipolar Junction Transistor (BJT) power device in the power amplifier.
2. The driver circuit of claim 1 further comprising a first resistor connecting a second terminal of the first current mirror and a third terminal of the first transistor in such a manner that the first current mirror mirrors the first current on to the first transistor, wherein the second terminal of the first transistor connects to the first terminal of the second transistor.
3. The driver circuit of claim 1 further comprising a second resistor connecting a second terminal of the second current mirror and a third terminal of the second transistor in such a manner that the second current mirror mirrors the second current on to the second transistor.
4. The driver circuit of claim 1 , wherein the first transistor, the second transistor, the first current mirror and the second current mirror correspond to at least one of: a Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) transistor, a Silicon-Germanium Bipolar Complementary Metal Oxide Semiconductor (SiGe BiCMOS) transistor, a Pseudomorphic High Electron Mobility Transistor (pHEMT), a Silicon on Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS) transistor and a Silicon on Insulator-Bipolar Complementary Metal Oxide Semiconductor (SOI-BiCMOS) transistor.
5. The driver circuit of claim 1 further comprising a first capacitor and a second capacitor connected in series to a third terminal of the first transistor and the third terminal of the second transistor.
6. The driver circuit of claim 5 , wherein adjusting the size of the first and the second capacitors provides the dynamic DC bias and the RF signal gain to the base terminal of the Bipolar Junction Transistor (BJT) power device in the power amplifier.
7. The driver circuit of claim 1 , wherein the first current source and the second current source comprises a Digital to Analog Converter (DAC) to control the first current and the second current, respectively.
8. The driver circuit of claim 1 further comprising:
a third transistor with a first terminal of the third transistor connected to the second terminal of the first transistor;
a fourth transistor with a first terminal of the fourth transistor connected to the first terminal of the second transistor, wherein a second terminal of the third transistor is connected to a second terminal of the fourth transistor;
a first delay element connected to a third terminal of the third transistor, a first control signal being fed to the first delay element; and
a second delay element connected to a third terminal of the fourth transistor, a second control signal being fed to the second delay element.
9. The driver circuit of claim 8 , wherein the first transistor and the third transistor are connected together in cascode configuration and the second transistor and the fourth transistor are connected together in cascode configuration.
10. The driver circuit of claim 9 , wherein the first transistor and the first current mirror are P-channel Metal Oxide Semiconductor (PMOS) transistors; and the second transistor and the second current mirror are N-channel Metal Oxide Semiconductor (NMOS) transistors.
11. The driver circuit of claim 8 , wherein the third transistor is P-channel Metal Oxide Semiconductor (PMOS) transistor; and the fourth transistor is N-channel Metal Oxide Semiconductor (NMOS) transistor.
12. The driver circuit of claim 1 , wherein the BJT is a Heterojunction Bipolar Transistor.
13. The driver circuit of claim 1 , wherein the BJT is a pseudomorphic High Electron Mobility Transistor.
14. The driver circuit of claim 7 , wherein a quiescent bias current for the Bipolar Junction Transistor (BJT) power device is set by adjusting a first DAC and a second DAC so that a DC bias current flows into the base of the BJT power device.
15. The driver circuit of claim 10 , wherein the dynamic DC bias current and RF signal to the Bipolar Junction Transistor (BJT) are controlled by a first control signal and a second control signal which adjust the size of the cascoded PMOS and the cascoded NMOS transistor respectively.
16. A driver circuit configured to provide dynamic DC bias and RF signal gain to a base terminal of a Bipolar Junction Transistor (BJT) power device in a power amplifier, the driver circuit comprising:
a first transistor with a first current flowing from a first terminal of the first transistor to a second terminal of the first transistor;
a second transistor with a second current flowing from a first terminal of the second transistor to a second terminal of the second transistor, wherein the first transistor and the second transistor are in a push-pull configuration;
a first current source connected to a first terminal of a first current mirror, wherein the first current source controls the first current; and
a second current source connected to a first terminal of a second current mirror, wherein the second current source controls the second current, and wherein the first current source and the second current source comprises a Digital to Analog Converter (DAC) to control the first current and the second current.
17. A driver circuit configured to provide dynamic DC bias and RF signal gain to a base terminal of a Bipolar Junction Transistor (BJT) power device in a power amplifier, the driver circuit comprising:
a first transistor with a first current flowing from a first terminal of the first transistor to a second terminal of the first transistor;
a second transistor with a second current flowing from a first terminal of the second transistor to a second terminal of the second transistor, wherein the first transistor and the second transistor are in a push-pull configuration;
a first current source connected to a first terminal of a first current mirror wherein the first current source controls the first current;
a second current source connected to a first terminal of a second current mirror, wherein the second current source controls the second current, the dynamic DC bias and RF signal gain corresponding to a difference between the first current and the second current; and
a first capacitor and a second capacitor connected in series to a third terminal of the first transistor and a third terminal of the second transistor, wherein adjusting the size of the first and the second capacitors provides the dynamic DC bias and the RF signal gain to the base terminal of the Bipolar Junction Transistor (BJT) power device in the power amplifier.