Efficient low-latency buffer

1. An application processor for reading and writing data from and to a bi-directional memory buffer, the application processor configured to:

responsive to an indication to write data to the bi-directional memory buffer, read a defined size of input data from the bi-directional memory buffer;

replace the input data read from the bi-directional memory buffer with output data of the defined size; and

responsive to a mode-change signal, change the defined size of data that is read and written from and to the bi-directional memory buffer, wherein the mode-change signal indicates one of a plurality of modes for the application processor to operate in, a first mode reading and writing a first size of data at a first rate, and a second mode reading and writing a second size of data greater than the first size of data at a second rate less than the first rate,

wherein:

in the first mode of operation the application processor receiving intermittently signals from a discontinuous interface at a first rate to provide a segment of data of a first predetermined size over a first data path connection to be stored in the bi-directional memory buffer; and

in the second mode of operation the application processor receiving intermittently signals from the discontinuous interface at a second data rate greater than the first data rate to read and replace a segment of data of a second predetermined size less than the first predetermined size over the first data path connection at a position in the bi-directional memory buffer;

wherein a continuous interface reads and replaces a block of data stored in the memory buffer over the second data path connection.

2. The application processor of claim 1 , further configured to receive the indication to write data from the bi-directional memory buffer.

3. The application processor of claim 1 , further configured to generate the indication to write data to the bi-directional memory buffer at a frequency inversely proportional to the defined size of data that is read from and written to the bi-directional memory buffer.

4. The application processor of claim 1 , further configured to process the read input data to identify one or more control commands.

5. The application processor of claim 1 wherein the indication to write data to the bi-directional memory buffer is received via an analog-to-digital/digital-to-analog converter (ADDAC) control signal line.

6. The application processor of claim 1 wherein:

the bi-directional memory buffer is of a predetermined size (b);

the first predetermined size is given by b minus a watermark (W) of the bi-directional memory buffer;

the second predetermined size is W;

a second pointer indicates a current read position (C) of the bi-directional memory buffer;

a first pointer indicates a replace position (S) of the bi-directional memory buffer;

in the first mode, the application processor signals to the discontinuous interface when (S-C) mod b is less than W; and

in the second mode, the application processor signals to the discontinuous interface when (C-S) mod b is greater than W,

wherein b is an integer greater than 1, W, C, and S are integers greater than or equal to 0.

7. An audio playback device comprising:

a bi-directional memory buffer; and

an application processor for reading and writing data from and to the bi-directional memory buffer, the application processor configured to:

responsive to an indication to write data to the bi-directional memory buffer, read a defined size of input data from the bi-directional memory buffer;

replace the input data read from the bi-directional memory buffer with output data of the defined size; and

responsive to a mode-change signal, change the defined size of data that is read and written from and to the bi-directional memory buffer, wherein the mode-change signal indicates one of a plurality of modes for the application processor to operate in, a first mode reading and writing a first size of data at a first rate, and a second mode reading and writing a second size of data greater than the first size of data at a second rate less than the first rate,

wherein:

in the first mode of operation the application processor receiving intermittently signals from a discontinuous interface at a first rate to provide a segment of data of a first predetermined size over a first data path connection to be stored in the bi-directional memory buffer; and

in the second mode of operation the application processor receiving intermittently signals from the discontinuous interface at a second data rate greater than the first data rate to read and replace a segment of data of a second predetermined size less than the first predetermined size over the first data path connection at a position in the bi-directional memory buffer;

wherein a continuous interface reads and replaces a block of data stored in the memory buffer over the second data path connection.

8. The audio playback device of claim 7 , wherein the application processor is further configured to receive the indication to write data from the bi-directional memory buffer.

9. The audio playback device of claim 7 , wherein the application processor is further configured to generate the indication to write data to the bi-directional memory buffer at a frequency inversely proportional to the defined size of data that is read from and written to the bi-directional memory buffer.

10. The audio playback device of claim 7 , wherein the application processor is further configured to process the read input data to identify one or more control commands.

11. The audio playback device of claim 7 , wherein:

the bi-directional memory buffer is of a predetermined size (b);

the first predetermined size is given by b minus a watermark (W) of the bi-directional memory buffer;

the second predetermined size is W;

a second pointer indicates a current read position (C) of the bi-directional memory buffer;

a first pointer indicates a replace position (S) of the bi-directional memory buffer;

in the first mode, the application processor signals to the discontinuous interface when (S-C) mod b is less than W; and

in the second mode, the application processor signals to the discontinuous interface when (C-S) mod b is greater than W,

wherein b is an integer greater than 1, W, C, and S are integers greater than or equal to 0.

12. The audio playback device of claim 7 , further comprising:

an input/output connection for connecting an input device and an output device to the audio playback device; and

an analog to digital converter and a digital to analog converter coupled between the input/output connection and the bi-directional memory buffer.

13. A method in an application processor for reading and writing data from and to a bi-directional memory buffer, the method comprising:

responsive to an indication to write data to the bi-directional memory buffer, reading a defined size of input data from the bi-directional memory buffer;

replacing the input data read from the bi-directional memory buffer with output data of the defined size; and

responsive to a mode-change signal, changing the defined size of data that is read and written from and to the bi-directional memory buffer, wherein the mode-change signal indicates one of a plurality of modes for the application processor to operate in, a first mode reading and writing a first size of data at a first rate, and a second mode reading and writing a second size of data greater than the first size of data at a second rate less than the first rate,

wherein:

in the first mode of operation the application processor receiving intermittently signals from a discontinuous interface at a first rate to provide a segment of data of a first predetermined size over a first data path connection to be stored in the bi-directional memory buffer; and

in the second mode of operation the application processor receiving intermittently signals from the discontinuous interface at a second data rate greater than the first data rate to read and replace a segment of data of a second predetermined size less than the first predetermined size over the first data path connection at a position in the bi-directional memory buffer;

wherein a continuous interface reads and replaces a block of data stored in the memory buffer over the second data path connection.

14. The method of claim 13 , further comprising receiving the indication to write data from the bi-directional memory buffer.

15. The method of claim 13 , further comprising generating the indication to write data to the bi-directional memory buffer at a frequency inversely proportional to the defined size of data that is read from and written to the bi-directional memory buffer.

16. The method of claim 13 , further comprising processing the read input data to identify one or more control commands.

17. The method of claim 13 , wherein:

the bi-directional memory buffer is of a predetermined size (b);

the first predetermined size is given by b minus a watermark (W) of the bi-directional memory buffer;

the second predetermined size is W;

a second pointer indicates a current read position (C) of the bi-directional memory buffer;

a first pointer indicates a replace position (S) of the bi-directional memory buffer;

in the first mode, the application processor signals to the discontinuous interface when (S-C) mod b is less than W; and

in the second mode, the application processor signals to the discontinuous interface when (C-S) mod b is greater than W,

wherein b is an integer greater than 1, W, C, and S are integers greater than or equal to 0.