Semiconductor device having level shift circuit

1. A semiconductor device comprising:

first and second level shift circuit units, each level shift circuit unit comprising:

first and second level shift circuits;

an input circuit that supplies complementary input signals to the first and second level shift circuits, respectively; and

an output circuit that converts complementary output signals supplied from the first and second level shift circuits into in-phase signals and short-circuits the in-phase signals;

an impedance control circuit that is coupled to generate output signals from short-circuited in-phase signals from each of the first and second level shift circuit units; and

an output buffer having an adjustable impedance that is coupled to receive the output signals from the impedance control circuit.

2. The semiconductor device as claimed in claim 1 , wherein

each of the first and second level shift circuits includes first and second transistors of first conductivity type that are cross-coupled to each other, and third and fourth transistors of second conductivity type that are coupled in series to the first and second transistors, respectively,

each of the first and second transistors has a power supply node coupled to a first power supply line,

each of the third and fourth transistors has a power supply node coupled to a second power supply line,

each of the third and fourth transistors has a control node supplied with an associated one of the complementary input signals,

one of the complementary output signals is output from one of a connecting node between the first and third transistors and a connecting node between the second and fourth transistors included in the first level shift circuit, and

the other of the complementary output signals is output from one of a connecting node between the first and third transistors and a connecting node between the second and fourth transistors included in the second level shift circuit.

3. The semiconductor device as claimed in claim 2 , wherein

each of the first and second level shift circuits further includes fifth and sixth transistors of the second conductivity type that are coupled in parallel with the first and second transistors, respectively,

the control node of the third transistor is short-circuited to that of the sixth transistor, and

the control node of the fourth transistor is short-circuited to that of the fifth transistor.

4. The semiconductor device as claimed in claim 2 , further comprising:

a DLL circuit that generates a first internal clock signal based on an external clock signal;

a clock dividing circuit that generates second and third internal clock signals having different phases based on the first internal clock signal; and

a multiplexer that outputs second and third internal data signals based on a first internal data signal in synchronization with one of the second and third clock signals,

wherein the level shift circuit unit is inserted into each of signal paths that transmit the second and third internal data signals, respectively.

5. The semiconductor device as claimed in claim 4 , wherein the multiplexer outputs fourth and fifth internal data signals in synchronization with the other of the second and third clock signals based on the sixth internal data signal that is supplied subsequent to the first internal data signal.

6. The semiconductor device as claimed in claim 4 , where the output buffer comprises:

a data output terminal;

a first output transistor of the first conductivity type that is coupled between the data output terminal and a third power supply line; and

a second output transistor of the second conductivity type that is coupled between the data output terminal and a fourth power supply line, wherein

the first output transistor is controlled by the second internal data signal that is passed through the level shift circuit unit, and

the second output transistor is controlled by the third internal data signal that is passed through the level shift circuit unit.

7. The semiconductor device as claimed in claim 6 , further comprising first to fourth power supply terminals that are coupled to the first to fourth power supply lines, respectively, wherein

the first and third power supply terminals are supplied with substantially the same potentials,

the second and fourth power supply terminals are supplied with substantially the same potentials,

the first and third power supply lines are separated from each other in the semiconductor device, and

the second and fourth power supply lines are separated from each other in the semiconductor device.

8. The semiconductor device as claimed in claim 4 , further comprising a plurality of power supply circuits each generating an internal power supply voltage,

wherein the internal power supply voltage supplied to the clock dividing circuit and the internal power supply voltage supplied to the multiplexer are generated by respective different power supply circuits and are separated from each other in the semiconductor device.

9. The semiconductor device as claimed in claim 8 , further comprising:

a memory cell array; and

a data transfer circuit that supplies the first internal data signal read from the memory cell array to the multiplexer, wherein

the plurality of power supply circuits includes first to third power supply circuits that generate first to third internal power supply voltages based on an external power supply voltage, respectively,

the first to third internal power supply voltages have substantially the same level and are separated from each other in the semiconductor device,

the data transfer circuit operates on the first internal power supply voltage,

the clock dividing circuit operates on the second internal power supply voltage, and

the multiplexer operates on the third internal power supply voltage.

10. The semiconductor device as claimed in claim 9 , further comprising a fourth power supply circuit that generates a fourth internal power supply voltage based on the external power supply voltage, wherein

the first to fourth internal power supply voltages have substantially the same level and are separated from each other in the semiconductor device, and

the DLL circuit includes a delay line that operates on the fourth internal power supply voltage.

11. The semiconductor device as claimed in claim 10 , further comprising a clock tree circuit that supplies the first internal clock signal generated by the DLL circuit to the clock dividing circuit,

wherein the clock tree circuit operates on the second internal power supply voltage.

12. The semiconductor device as claimed in claim 1 , wherein the first level shift circuit has substantially the same circuit configuration as that of the second level shift circuit.

13. A device comprising:

an input terminal;

an output terminal;

a first level shift circuit including an input node, that is coupled to the input terminal, and an output node;

a second level shift circuit including an output node, that is coupled to the output terminal, and an input node;

a first inverting circuit coupled between the output node of the first level shift circuit and the output terminal;

a second inverting circuit coupled between the input terminal and the input node of the second level shift circuit;

an impedance control circuit that is coupled to the output terminal for generating output signals therefrom; and

an output buffer having an adjustable impedance that is coupled to receive the output signals from the impedance control circuit.

14. The device as claimed in claim 13 , wherein each of the first and second level shift circuits comprises:

a first transistor coupled between a first power line and a first circuit node and including a control electrode coupled to a second circuit node, the second circuit node being coupled to the output node;

a second transistor coupled between the first power line and the second circuit node and including a control electrode coupled to the first circuit node;

a third transistor coupled between the first circuit node and a second power line and including a control electrode coupled to the input node;

a fourth transistor coupled between the second circuit node and the second power line and including a control electrode; and

a first inverter coupled between the input node and the control electrode of the fourth transistor.

15. The device as claimed in claim 14 , wherein each of the first and second level shift circuit further comprises a second inverter inserted between the second circuit node and the output node.

16. The device as claimed in claim 14 , wherein each of the first and second level shift circuit further comprises fifth transistor coupled between the first power line and the first circuit node and including a control electrode coupled to the control electrode of the fourth transistor and a sixth transistor coupled between the first power line and the second circuit node and including a control electrode coupled to the control electrode of the third transistor.

17. The device as claimed in claim 16 , wherein each of the first and second level shift circuit further comprises a second inverter inserted between the second circuit node and the output node.

18. The device as claimed in claim 14 , wherein each of the first and second level shift circuits further comprises a fifth transistor intervening between the first power line and each of the first and second transistors.

19. The device as claimed in claim 18 , wherein each of the first and second level shift circuit further comprises a second inverter inserted between the second circuit node and the output node.

20. The device as claimed in claim 14 , wherein the first inverter operates on a power voltage that is different from a voltage supplied to the first power line.