Successive approximation analog-to-digital conversion

1. An analog-to-digital converter (ADC) circuit to convert an analog input signal to a digital output signal, the ADC circuit comprising:

a current mode (CM) digital-to-analog converter (DAC) circuit configured to provide a DAC current;

a sample and hold (SH) circuit configured to derive a sampled-input signal from the analog input signal;

a transconductance circuit configured to derive an input current from the sampled-input signal;

a comparator circuit configured to generate a comparator signal in response to an error signal determined based on the DAC current and the input current; and

a successive approximation register (SAR) circuit configured to receive the comparator signal and to generate at least one of a DAC-code signal or the digital output signal,

wherein the CM DAC circuit is configured to use the DAC-code signal to control the DAC current.

2. The ADC circuit of claim 1 , wherein the CM DAC circuit comprises a decoder circuit configured to decode the DAC-code signal into a control signal.

3. The ADC circuit of claim 2 , wherein the CM DAC circuit is configured to use the control signal to control the DAC current.

4. The ADC circuit of claim 2 , wherein the CM DAC circuit comprises a plurality of current sources, and wherein at least one of the plurality of current sources is configured to provide the DAC current, based on the control signal.

5. The ADC circuit of claim 1 , wherein the CM DAC circuit is configured to provide the DAC current through a first cascode circuit, and wherein the DAC current is a differential current.

6. The ADC circuit of claim 1 , further comprising an error circuit configured to provide a voltage error signal determined based on a difference between the DAC current and the input current, and wherein the error circuit comprises a switch to reduce glitches in the voltage error signal.

7. The ADC circuit of claim 1 , wherein the transconductance circuit is configured to provide a differential input current through a second cascode circuit.

8. The ADC circuit of claim 1 , wherein the SAR circuit is configured to generate the digital output signal at a last cycle of a plurality of SAR cycles.

9. The ADC circuit of claim 1 , wherein the SAR circuit is configured to generate, at a first cycle of a plurality of SAR cycles, the DAC-code signal that comprises a mid-code.

10. An analog-to-digital converter (ADC) circuit to convert an analog input signal to a digital output signal, the ADC circuit comprising:

a current mode (CM) digital-to-analog converter (DAC) circuit configured to provide a DAC current through a first cascode circuit;

a comparator circuit configured to generate a comparator signal in response to an error signal determined based on the DAC current and the analog input signal; and

a successive approximation register (SAR) circuit configured to generate at least one of a DAC-code signal or the digital output signal, in response to the comparator signal,

wherein the CM DAC circuit is configured to use the DAC-code signal to control the DAC current,

wherein the DAC current is a differential current.

11. A method of converting an analog input signal to a digital output signal, the method comprising:

operating a successive approximation analog-to-digital converter (ADC) circuit in a current-conversion mode by:

deriving an input current based on the analog input signal;

operating a current mode (CM) digital-to-analog converter (DAC) circuit to provide a DAC current through a first cascode circuit;

generating a comparator signal in response to an error signal determined based on the DAC current and the input current; and

receiving the comparator signal and generating at least one of a DAC-code signal or the digital output signal,

wherein operating the CM DAC circuit includes controlling the DAC current by using the DAC-code signal, and wherein the DAC current is a differential current.

12. The method of claim 11 , wherein operating the CM DAC circuit comprises decoding the DAC-code signal into a control signal.

13. The method of claim 12 , wherein operating the CM DAC circuit comprises using the control signal to control the DAC current.

14. The method of claim 12 , wherein operating the CM DAC circuit comprises operating a plurality of current sources, and further comprising operating at least one of the plurality of current sources to provide the DAC current, based on the control signal.

15. The method of claim 11 , further comprising providing a voltage error signal determined based on a difference between the DAC current and the input current and wherein providing the voltage error signal comprises operating a switch to reduce glitches in the voltage error signal.

16. The method of claim 11 , wherein deriving the input current comprises deriving the input current from a sampled-input signal provided.

17. An apparatus for converting an analog input signal to a digital output signal, the apparatus comprising:

means for providing a DAC current;

means for generating a comparator signal in response to an error signal determined based on the DAC current and the analog input signal; and

means for generating at least one of a DAC-code signal or the digital output signal, in response to the comparator signal,

wherein the means for providing the DAC current comprises a first cascode circuit, and the means for providing the DAC current is configured to use the DAC-code signal to control the DAC current, and wherein the DAC current is a differential current.