Semiconductor device having plural memory chip
View Patent ↗A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions.
1. A semiconductor device comprising
a plurality of memory chips stacked to each other,
each of the memory chips including a plurality of memory banks, a plurality of read/write buses each transferring data to/from an associated one of the memory banks, and
a plurality of penetration electrodes each transferring the data to/from an associated one of the read/write buses and arranged penetrating through the memory chip,
the penetration electrodes arranged in the same positions as seen in a stacking direction of the memory chips being coupled in common between the memory chips, and
each one of the memory banks included in the memory chips being activated in response to an access request so that the activated memory banks are arranged in respective different positions as seen in the stacking direction, thereby the data are simultaneously transferred via the penetration electrodes in parallel.
2. The semiconductor device as claimed in claim 1 , wherein the access request is made by supplying an address signal and a command signal to the memory chips in common.
3. The semiconductor device as claimed in claim 2 , wherein each of the chips has respective one of chip addresses different from each other, the address signal includes a bank address that specifies one of the memory banks, each of the memory chips further includes a bank address generating circuit that performs a logical operation using the bank address and the chip address to generate an internal bank address, and each of the memory chips activates any one of the memory banks based on the internal bank address.
4. The semiconductor device as claimed in claim 3 , wherein each of the memory chips further includes a chip address register that retains the chip address, and the chip address registers included in the memory chips are serially connected via other penetration electrodes.
5. The semiconductor device as claimed in claim 1 , further comprising an interface chip that controls the memory chips, wherein the interface chip converts the data supplied from the memory chips via the penetration electrodes from parallel to serial and outputs the data serial converted to outside, and the interface chip converts the data supplied from outside from serial to parallel and outputs the data parallel converted to the memory chips via the penetration electrodes.
6. The semiconductor device as claimed in claim 5 , wherein the memory chips and the interface chip are stacked to one another.
7. The semiconductor device as claimed in claim 1 , wherein the same addresses are assigned to the memory chips so that all the memory chips are accessed at the same time.
8. The semiconductor device as claimed in claim 1 , wherein the memory chips include a plurality of groups of memory chips, and the same addresses are assigned to the memory chips belonging to the same group so that all the memory chips belonging to the same group are accessed at the same time.