Input/output circuit
View Patent ↗An output transistor bias generation circuit which applies a bias voltage to one of two NMOS transistors constituting an output circuit having a stack structure, includes diode-connected NMOS transistors provided between an external connection pad connected to an external signal line having a voltage higher than a power supply voltage of an LSI circuit, and the gate of an NMOS transistor, diode-connected NMOS transistors provided between the gate of the NMOS transistor and a ground line, a diode-connected NMOS transistor provided between the power supply line and the gate of the NMOS transistor, and a capacitor-connected NMOS transistor provided between the gate of the NMOS transistor and the ground line.
1. An input/output circuit for an LSI circuit having an external connection pad, comprising:
an input circuit connected to the external connection pad; and
an output circuit connected to the external connection pad, wherein
the output circuit includes
a first and a second N-channel MOS transistor provided between the external connection pad and a ground line of the LSI circuit, and connected together in series, where the first N-channel MOS transistor is closer to the external connection pad and the second N-channel MOS transistor is closer to the ground line, and
an output transistor bias generation circuit configured to supply, to the gate of the first N-channel MOS transistor, a voltage which is determined by a voltage of the external connection pad and a voltage of a power supply line of the LSI circuit, and
the output transistor bias generation circuit includes
a first diode element provided between the external connection pad and the gate of the first N-channel MOS transistor,
a second diode element provided between the gate of the first N-channel MOS transistor and the ground line,
a third diode element provided between the power supply line and the gate of the first N-channel MOS transistor, and
a capacitive element provided between the gate of the first N-channel MOS transistor and the ground line.
2. The input/output circuit of claim 1 , wherein
the first diode element includes two diode-connected MOS transistors connected together in series,
the second diode element includes three diode-connected MOS transistors connected together in series, and
the third diode element includes one diode-connected MOS transistor.
3. The input/output circuit of claim 2 , wherein
the MOS transistors included in the first, second, and third diode elements all have the same gate length and gate width.
4. The input/output circuit of claim 1 , wherein
the capacitive element is a MOS transistor whose gate is connected to the gate of the first N-channel MOS transistor and whose drain and source are connected to the ground line.
5. The input/output circuit of claim 1 , wherein
the output transistor bias generation circuit further includes a resistive element provided between at least one of the first, second and third diode elements and the gate of the first N-channel MOS transistor.
6. The input/output circuit of claim 1 , wherein
the output transistor bias generation circuit further includes a resistive element provided between the external connection pad and the first diode element.
7. The input/output circuit of claim 1 , wherein
the output circuit further includes an input terminal connected to the gate of the second N-channel MOS transistor, and
a ground potential is output to the external connection pad by the second N-channel MOS transistor, depending on a state of the input terminal.
8. The input/output circuit of claim 1 , wherein
the input circuit includes
a third N-channel MOS transistor whose drain is connected to the external connection pad,
an input buffer whose input terminal is connected to the source of the third N-channel MOS transistor, and
an input transistor bias generation circuit configured to supply, to the gate of the third N-channel MOS transistor, a voltage which is determined based on the voltage of the external connection pad and the voltage of the power supply line.
9. The input/output circuit of claim 8 , wherein
the input transistor bias generation circuit includes
a first resistive element provided between the external connection pad and the drain of the third N-channel MOS transistor,
a fourth diode element between the drain of the third N-channel MOS transistor and the gate of the third N-channel MOS transistor, and
a second resistive element provided between the power supply line and the gate of the third N-channel MOS transistor.
10. The input/output circuit of claim 9 , wherein
the fourth diode element includes two diode-connected MOS transistors connected together in series.
11. The input/output circuit of claim 8 , wherein
the third N-channel MOS transistor has a gate width of 1 μm or less.
12. The input/output circuit of claim 1 , wherein
the first diode element includes three diode-connected MOS transistors connected together in series,
the second diode element includes three diode-connected MOS transistors connected together in series,
the third diode element includes one diode-connected MOS transistor.
13. The input/output circuit of claim 12 , wherein
the MOS transistors included in the first, second, and third diode elements all have the same gate length and gate width.
14. The input/output circuit of claim 1 , wherein
the first N-channel MOS transistor includes two N-channel MOS transistors connected together in series.
15. The input/output circuit of claim 1 , further comprising:
an ESD protective circuit provided between the external connection pad and the ground line.
16. The input/output circuit of claim 15 , wherein
the ESD protective circuit includes a bipolar transistor.
17. The input/output circuit of claim 15 , wherein
the ESD protective circuit includes a thyristor circuit.