Low power level shifter with output swing control
View Patent ↗A level shifter comprising a first driver transistor receiving an input signal. A gate-controlled transistor coupled to the first driver transistor. A second driver transistor coupled to the gate controlled transistor. An output coupled to the second driver transistor, wherein the gate-controlled transistor is for receiving a predetermined gate voltage when the output voltage exceeds a predetermined value.
1. A level shifter comprising:
a first driver transistor configured to receive an input signal;
a gate-controlled transistor coupled to the first driver transistor;
a second driver transistor coupled to the gate controlled transistor;
a half cycle control coupled to the level shifter, wherein the half cycle control is configured to generate a gate voltage to be applied to the gate-controlled transistor for a duration of one half cycle of a predetermined cycle; and
an output coupled to the second driver transistor;
wherein the gate-controlled transistor is configured to receive a predetermined gate voltage when the output voltage exceeds a predetermined value.
2. The level shifter of claim 1 wherein the first driver transistor is an NFET and the gate controlled transistor and the second driver transistor are both PFETs.
3. The level shifter of claim 1 wherein the second driver transistor is a PFET and the gate controlled transistor and the first driver transistor are both NFETs.
4. The level shifter of claim 1 further comprising a dynamic gate controller coupled to the level shifter, wherein the dynamic gate controller is configured to generate the gate voltage to be applied to the gate-controlled transistor.
5. The level shifter of claim 1 further comprising a full cycle control coupled to the level shifter, wherein the full cycle control is configured to generate the gate voltage to be applied to the gate-controlled transistor for a duration of one full cycle.
6. The level shifter of claim 1 further comprising a variable gate control voltage coupled to the level shifter, wherein the variable gate control voltage is configured to generate a variable gate voltage to be applied to the gate-controlled transistor.
7. The level shifter of claim 1 wherein the first driver transistor is an NFET, the gate controlled transistor and the second driver transistor are both PFETs, and further comprising a dynamic gate controller coupled to the level shifter, wherein the dynamic gate controller is configured to generate the gate voltage to be applied to the gate-controlled transistor.
8. The level shifter of claim 1 wherein the second driver transistor is a PFET and the gate controlled transistor and the first driver transistor are both NFETs, and further comprising a dynamic gate controller coupled to the level shifter, wherein the dynamic gate controller is configured to generate the gate voltage to be applied to the gate-controlled transistor.
9. The level shifter of claim 1 further comprising:
a full cycle control coupled to the level shifter, wherein the full cycle control is configured to generate the gate voltage to be applied to the gate-controlled transistor for a duration of one full cycle; and
a variable gate control voltage coupled to the level shifter, wherein the variable gate control voltage is configured to generate a variable gate voltage to be applied to the gate-controlled transistor.
10. A level shifter comprising:
an NFET driver transistor for receiving an input signal;
a PFET gate-controlled transistor coupled to the NFET driver transistor;
a PFET driver transistor coupled to the gate controlled transistor;
a full cycle control coupled to the level shifter, wherein the full cycle control is configured to generate a gate voltage to be applied to the gate-controlled transistor for a duration of one full cycle of a predetermined cycle; and
an output coupled to the PFET driver transistor;
wherein the gate-controlled transistor is configured to receive a predetermined gate voltage when the output voltage exceeds a predetermined value.
11. The level shifter of claim 10 further comprising a dynamic gate controller coupled to the level shifter, wherein the dynamic gate controller is configured to generate the gate voltage to be applied to the gate-controlled transistor.
12. The level shifter of claim 10 further comprising a half cycle control coupled to the level shifter, wherein the half cycle control is configured to generate the gate voltage to be applied to the gate-controlled transistor for a duration of one half cycle.
13. The level shifter of claim 10 further comprising a variable gate control voltage coupled to the level shifter, wherein the variable gate control voltage is configured to generate a variable gate voltage to be applied to the gate-controlled transistor.
14. The level shifter of claim 10 further comprising:
a dynamic gate controller coupled to the level shifter, wherein the dynamic gate controller is configured to generate the gate voltage to be applied to the gate-controlled transistor; and
a variable gate control voltage coupled to the level shifter, wherein the variable gate control voltage is configured to generate a variable gate voltage to be applied to the gate-controlled transistor.
15. The level shifter of claim 10 further comprising:
a half cycle control coupled to the level shifter, wherein the half cycle control is configured to generate the gate voltage to be applied to the gate-controlled transistor for a duration of one half cycle; and
a variable gate control voltage coupled to the level shifter, wherein the variable gate control voltage is configured to generate a variable gate voltage to be applied to the gate-controlled transistor.
16. A level shifter comprising:
a pair of driver transistors for receiving an input signal and generating an output signal;
a variable gate control voltage coupled to the level shifter, wherein the variable gate control voltage is configured to generate a variable gate control voltage to be applied to the level shifter; and
a half cycle control coupled to the level shifter, wherein the half cycle control is configured to generate the gate control voltage for a duration of one half cycle of a predetermined cycle.
17. The level shifter of claim 16 further comprising:
a second pair of driver transistors configured to receive the input signal and to generate the output signal.
18. The level shifter of claim 16 further comprising a full cycle control coupled to the level shifter, wherein the full cycle control is configured to generate the gate control voltage to be applied for a duration of one full cycle of a predetermined cycle.
19. The level shifter of claim 16 further comprising a fixed gate control voltage coupled to the level shifter, wherein the fixed gate control voltage is configured to generate a fixed gate control voltage to be applied to the level shifter.