IP Library Granted Patent US 8,735,982
Granted Patent B2
US 8,735,982 · App. 13/290,508 · Granted May 27, 2014

Semiconductor device with superjunction structure

Inventor: Yasuhiko Onishi (Matsumoto, JP)
Assignee: Fuji Electric Co., Ltd.
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Quick Facts
Patent No.
US 8,735,982
App. No.
13/290,508
Granted
May 27, 2014
Kind
B2
Abstract

A superjunction semiconductor device is disclosed which has, in the active section, a first alternating-conductivity-type layer which makes a current flow in the ON-state of the device and sustains a bias voltage in the OFF-state of the device. There is a second alternating-conductivity-type layer in a edge-termination section surrounding the active section. The width of a region of a second conductivity type in the second alternating-conductivity-type layer becomes narrower at a predetermined rate from the edge on the active section side toward the edge of the edge termination section. The superjunction semiconductor device facilitates manufacturing the edge-termination section which exhibits a high breakdown voltage and a high reliability for breakdown voltage through a process that exhibits a high mass-productivity.

Claims (10)

1. A semiconductor device comprising:

a heavily doped semiconductor substrate of a first conductivity type;

a first alternating-conductivity-type layer comprising a column-shaped or a layer-shaped first semiconductor region of the first conductivity type and a column-shaped or a layer-shaped second semiconductor region of a second conductivity type, the first and second semiconductor regions adjoining each other and repeating in parallel to a surface of the semiconductor substrate in order to form a pn-junction, wherein the pn-junctions extend perpendicularly to the surface of the semiconductor substrate and wherein the first alternating-conductivity-type layer is a drift layer that makes a current flow in an ON-state of the semiconductor device and sustains a voltage in an OFF-state of the semiconductor device;

a surface structure on a surface side of the first alternating-conductivity-type layer, the surface structure constituting an active section that makes the current flow;

an edge-termination section surrounding the active section;

a second alternating-conductivity-type layer in the edge-termination section, the second alternating-conductivity-type layer comprising a column-shaped fourth semiconductor region of the second conductivity type in a third semiconductor region of the first conductivity type, the third and fourth semiconductor regions adjoining each other and repeating in parallel to the surface of the semiconductor substrate to form a pn-junction, wherein the pn-junctions extend perpendicularly to the surface of the semiconductor substrate;

wherein a width of the fourth semiconductor region in the second alternating-conductivity-type layer becomes narrower at a predetermined rate from an edge on a side of the active section toward an edge of the edge termination section.

2. The semiconductor device according to claim 1 , further comprising guard rings in a surface portion of the second alternating-conductivity-type layer, the guard rings being spaced apart from each other.

3. The semiconductor device according to claim 1 , further comprising guard rings and electrically conductive field plates on the guard rings, the field plates being in electrical contact with the guard rings.

4. The semiconductor device according to claim 1 , wherein the pitch of the alternating first and second type regions in the active section is the same as the pitch of the third and fourth semiconductor regions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2011
From: ONISHI, YASUHIKO
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 027345/0033 →
Priority Claims (1)
JP 2010-250427 · Nov 9, 2010 · national
Continuity (1)
Related Publication 20120112306A1 · May 10, 2012